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copyright ?2006 genesis microchip inc. all rights reserved . including the right of reproduction in whole or in part in any form. even though genesis microchip inc. has reviewed this publicati on, genesis microchip inc. makes no warranty or representation, e ither express or implied, with respect to this publication, its quality, accuracy, noninfringment, merchantability, or fitness for a particular purpose. as a result, this publication is provided ?as is? and the reader assumes the risk as to its quality, accuracy, or suitability for any particular purpose. in no event will genesis microchip inc. be liable for direct, indirect, special, incidental, or consequential damages resulting from any defect or inaccuracy in this publication, even if advised of the possibility of such damages. this publication is provided with restricted rights. use, duplica tion, or disclosure by the govern ment are subject to restricti ons set forth in dfars 252.277-7013 or 48 cfr 52.227-19 as applicable. the genesis logo is a trademark of genesis microchip inc. all other marks, brands and product names are the property of their respective owners. GM5862H/gm5822h preliminary datasheet ordering information part number output resolution package temperature range GM5862H-lf (1) wuxga (1920x1200) gm5822h-lf wsxga+ (1680x1050) 256-pin pqfp lead free 0-70c note (1): hdcp enabled parts are only sold to hdcp licensed customers. genesis microchip confidential p/n c5862-dat-01c www.gnss.com free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 2 revision history revision date description c5862-dat-01a january 2006 initial release c5862-dat-01b january 2006 updated tables 25, 26, and 30 c5862-dat-01c february 2006 changed min sampling frequency in table 20 changed power consumption speed, table 26 free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 3 contents 1 overview....................................................................................................................... ...........5 1.1 system design example........................................................................................................5 1.2 features ....................................................................................................................... ..........6 2 pin diagram.................................................................................................................... .........7 3 pin list ....................................................................................................................... ................8 4 functional description ...............................................................................................16 4.1 bootstrap conf iguration ......................................................................................................16 4.2 chip initia lizatio n............................................................................................................ ....18 4.2.1 power sequencing .........................................................................................................18 4.2.2 hardware reset ............................................................................................................19 4.3 clock generation............................................................................................................... ..21 4.3.1 using the internal oscillator with external crystal ...........................................................21 4.3.2 clock synthesis ............................................................................................................23 4.4 analog input port (aip) ......................................................................................................23 4.4.1 analog to digital converter (adc) ................................................................................24 4.4.2 schmitt trigger .............................................................................................................25 4.4.3 dc restoration .............................................................................................................26 4.4.4 sync extraction ............................................................................................................26 4.4.5 adc characteristics ......................................................................................................27 4.4.6 clock recovery circuit .................................................................................................27 4.4.7 sampling phase adjustment ...........................................................................................28 4.4.8 adc capture window ..................................................................................................28 4.5 digital visual interf ace (dvi) input port............................................................................29 4.5.1 dvi receiver characteristics .........................................................................................29 4.5.2 high-bandwidth digital content protection (hdcp) ........................................................29 free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 4 4.6 video input port for itu656 sources (vip) .......................................................................29 4.7 16-bit ttl input............................................................................................................... ...30 4.8 test pattern generator (tpg)..............................................................................................30 4.9 input format m easurement .................................................................................................31 4.10 hsync / vsync delay ....................................................................................................31 4.11 horizontal and verti cal measurement.................................................................................32 4.12 format change detectio n....................................................................................................32 4.13 ifm watc hdog ................................................................................................................... .32 4.14 internal odd/even field detection......................................................................................33 4.15 input pixel me asurement.....................................................................................................33 4.16 image boundary detection..................................................................................................33 4.17 image auto balance ............................................................................................................3 3 4.18 instant auto? .................................................................................................................. ...34 4.19 intelligent image processi ng ...............................................................................................34 4.20 advanced digital color controls ........................................................................................36 4.21 video enhancement ............................................................................................................37 4.22 external memory interface..................................................................................................38 4.23 frame rate c onversion .......................................................................................................39 4.24 picture-in-picture ? pi p channel pr ocessing ......................................................................39 4.25 output display port (odp) .................................................................................................40 4.26 energy spectrum mana gement? (esm).............................................................................43 4.27 on-screen disp lay (osd)...................................................................................................43 4.28 on-chip microcontr oller (ocm) ........................................................................................45 4.29 electrostatic disc harge (esd).............................................................................................49 5 electrical spec ifications .........................................................................................50 5.1 preliminary dc ch aracteris tics ...........................................................................................50 5.2 preliminary ac ch aracteris tics ...........................................................................................51 6 branding information ..................................................................................................55 7 mechanical specifications........................................................................................56 8 solder pr ofiles ................................................................................................................ .58 ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 5 1 overview the ? GM5862H ? and ? derivative ? devices ? are ? a ? highly ? integrated ? mixed ? signal ? lcd ? controller ? for ? multi \ function ? lcd ? monitors ? and ? lcd ? tv ? applications ? supporting ? up ? to ? wuxga ? resolutions. ? the ? GM5862H ? has ? a ? proven ? adc/pll ? and ? ultra \ reliable ? dvi? ? compatible ? digital ? receiver ? with ? frame ? rate ? conversion ? to ? ensure ? proven ? pc ? graphics ? compatibility. ?? adaptive ? contrast ? and ? color ? (acc) ? and ? active ? color ? management ? three ? dimension ? (acm \ 3d), ? coupled ? with ? response ? time ? compensation ? provide ? superior ? image ? quality. ?? with ? integrated ? picture \ in \ picture, ? embedded ? microcontroller, ? versatile ? osd ? engine, ? low ? bandwidth ? general ? purpose ? adc ? and ? dual ? lvds ? transmitters ? (or ? optional ? ttl ? output), ? the ? GM5862H ? family ? devices ? enable ? cost ? effective ? high ? resolution ? lcd ? monitor ? solutions. ? 1.1 system design example designs ? based ? on ? the ? GM5862H ? have ? reduced ? system ? cost, ? simplified ? hardware ? and ? firmware ? design ? and ? increased ? reliability ? due ? to ? the ? minimal ? number ? of ? components ? required ? in ? the ? system. ? figure 1: multi-function lcd monitor system design example ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 6 1.2 features d ual a nalog i nput ? operation up to 205mhz ? dual rgb inputs ? single rgb & single ypbpr up to 1080i inputs ? bi-level and tri-level analog sync support and macrovision support ? dual hsync, vsync and sog inputs u ltra -r eliable dvi i nput ? operation up to 165mhz ? direct connect to all dvi compliant digital transmitters ? high-bandwidth digital content protection d igital v ideo i nput ? itu656 video input support for direct connect to commercially available video decoder ? itu601 (16-bit) video input support for external mpeg2 decoder, dvi rx and adc h igh q uality a dvanced s caling e ngine ? independent and programmable h & v scaling factors ? panoramic scaling (non-linear) ? variable sharpness settings p icture - in -p icture (pip) ? variable pip window si ze up to 640x480 ? side by side widow up to 960x600 ? video pip on graphics/graphics pip on video ? independent pip window color controls a dvanced d igital c olor c ontrols ? adaptive contrast and color and active color management three dimension f rame r ate c onversion (frc) ? 16-bit/32-bit data path to support single or dual 1mx16 sdr sdram ? full frame rate conversion up to sxga 75hz r esponse t ime c ompensation ? compensates motion blur that results from slow response time of lcd panels ? resulting in motion image that is clean and crisp osd c ontroller ? up to 4 windows: 1, 2 or 4-bits per pixel color ? blinking, transparency, blending and proportional fonts support o utput s upport ? dual channel lvds transmitters with pin swap for flexibility in pcb layout ? optional 24-bit ttl s ystem - on -c hip integration for l ower b o m ? on-chip reset circuit wi th integrated schmitt trigger for hsync and vsync ? embedded x86 mcu with serial interface ? general purpose low bandwidth adc ? integrated gamma and 3x3 lut for srgb compliance ? esm? and boundary scan support ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 7 2 pin diagram the ? GM5862H ? is ? packaged ? in ? a ? 256 \ pin ? plastic ? quad ? flat ? pack ? (pqfp). ?? figure 2: GM5862H/gm5822h pinout ? 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 vssa_adc red1+ vdda_adc_33 green1+ sogmcss1 vdda_adc_33 blue1+ vssa_adc red- green- blue- vssa_adc red2+ vssa_adc green2+ sogmcss2 vdda_adc_33 blue2+ vssa_adc vsync1 hsync1 crvss cvdd_18 vsync2 hsync2 rvdd_33 gpio_48 gpio_49 gpio_2 gpio_3/jtag_reset crvss rvdd_33 gpio_4/jtag_tdo gpio_5/jtag_tdi gpio_6/jtag_clk gpio_7/jtag_mode crvss uart_do/boot[3] uart_di ddc_sda_ch1 ddc_scl_ch1 rvdd_33 crvss ddc_sda_ch2 ddc_scl_ch2 vdd_dvi_18 vss_dvi rxc- rxc+ vdda_dvi_33 rx0- rx0+ vssa_dvi vdd_dvi_18 vssa_dvi rx1- rx1+ vdda_dvi_33 rx2- rx2+ vssa_dvi vdd_dvi_18 rext vssa_dvi rvdd_33 cvdd_18 crvss dqm gpo_0 gpo_1 gpo_2 gpo_3 crvss gpo_4 gpo_5 nc gpo_6 crvss ppwr pbias avdd_lv_33 avss_lv avdd_out_lv_33 ch3p_lv_e/r0 ch3n_lv_e/r1 clkp_lv_e/r2 clkn_lv_e/r3 ch2p_lv_e/r4 ch2n_lv_e/r5 ch1p_lv_e/r6 ch1n_lv_e/r7 ch0p_lv_e/g0 ch0n_lv_e/g1 avss_out_lv avdd_out_lv_33 ch3p_lv_o/g2 ch3n_lv_o/g3 clkp_lv_o/g4 clkn_lv_o/g5 ch2p_lv_o/g6 ch2n_lv_o/g7 ch1p_lv_o/b0 ch1n_lv_o/b1 ch0p_lv_o/b2 ch0n_lv_o/b3 avss_out_lv avdd_out_lv_33 gpio_10/b4 gpio_11/b5 gpio_12/b6 gpio_13/b7 crvss cvdd_18 rvdd_33 gpio_14/dclk gpio_15/den gpio_16/dhs gpio_17/dvs gpio_18/scl_0(2w_mst) gpio_19/sda_0(2w_mst) gpio_20/scl_1(2w_mst) gpio_21/sda_1(2w_mst) cvdd_18 crvss scan_en gpo_7 nc nc 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 itu601_5/gpio_37 itu601_6/gpio_38 itu601_7/gpio_39 itu601_8/gpio_40 itu601_9/gpio_41 itu601_10/gpio_42 itu601_11/gpio_43 itu601_12/gpio_44 itu601_13/gpio_45 rvdd_33 cvdd_18 crvss gpo_9/pwm3/boot[7] gpo_8/pwm2/boot[6] pwm1//boot[4] pwm0/boot[5] itu601_14/gpio_46 itu601_15/gpio_47 itu601_vs itu601_hs crvss cvdd_18 itu601_clk itu601_fld itu601_de gpio_1/ddc_sda_0 gpio_0/ddc_scl_0 spi_do/boot[2] spi_di spi_clk/boot[1] spi_csn/boot[0] crvss rvdd_33 vclk gpio_31/vda[7] gpio_30/vda[6] gpio_29/vda[5] gpio_28/vda[4] gpio_27/vda[3] gpio_26/vda[2] gpio_25/vda[1] gpio_24/vda[0] gpio_23/int0 cvdd_18 crvss gpio_22/int1 jtag_bs_en lbadc_vdd_33 lbadc_in1 lbadc_in2 lbadc_in3 lbadc_rtn/gnd resetn avdd_rpll_33 tclk xtal vss_rpll vdd_rpll_18 vbufc_rpll vdd1_adc_18 vss1_adc nc nc nc crvss itu601_4/gpio_36 itu601_3/gpio_35 itu601_2/gpio_34 itu601_1/gpio_33 itu601_0/gpio_32 rvdd_33 dq7_a dq6_a dq5_a dq4_a dq3_a dq2_a crvss dq1_a dq0_a dq15_a dq14_a dq13_a dq12_a dq11_a dq10_a dq9_a dq8_a crvss rvdd_33 we# cas# ras# cvdd_18 ba mclk a9 crvss rvdd_33 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 rvdd_33 crvss dq7_b dq6_b dq5_b dq4_b dq3_b dq2_b dq1_b dq0_b dq15_b crvss dq14_b dq13_b dq12_b dq11_b dq10_b dq9_b dq8_b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 8 3 pin list i/o legend: a = analog, i = input, o = output, p = power, g = ground note: all ground pins to be connected to a single contiguous ground plane (system ground). table 1: lvds panel interface pin name no i/o description avdd_lv_3.3 81 ap 3.3v supply for lvds pll and bandgap. bypass to system ground wi th a 0.1uf capacitor. avss_lv 82 ag ground for lvds pll and bandgap. tie directly to system ground. avdd_out_lv_3.3 83 ap 3.3v supply for lvds/ttl outputs. bypass to system ground with a 0.1uf capacitor. ch3p_lv_e/r0 84 ao lvds data, shared with lvttl display port r0 ch3n_lv_e/r1 85 ao lvds data, shared with lvttl display port r1 clkp_lv_e/r2 86 ao lvds clock+, shared with lvttl display port r2 clkn_lv_e/r3 87 ao lvds clock-, shared with lvttl display port r3 ch2p_lv_e/r4 88 ao lvds data, shared with lvttl display port r4 ch2n_lv_e/r5 89 ao lvds data, shared with lvttl display port r5 ch1p_lv_e/r6 90 ao lvds data, shared with lvttl display port r6 ch1n_lv_e/r7 91 ao lvds data, shared with lvttl display port r7 ch0p_lv_e/g0 92 ao lvds data, shared with lvttl display port g0 ch0n_lv_e/g1 93 ao lvds data, shared with lvttl display port g1 avss_out_lv 94 ag ground for lvds/ttl outpu ts. tie directly to system ground. avdd_out_lv_3.3 95 ap 3.3v supply for lvds/ttl outputs. bypass to system ground with a 0.1uf capacitor. ch3p_lv_o/g2 96 ao lvds data, shared with lvttl display port g2 ch3n_lv_o/g3 97 ao lvds data, shared with lvttl display port g3 clkp_lv_o/g4 98 ao lvds clock+, shared with lvttl display port g4 clkn_lv_o/g5 99 ao lvds clock-, shared with lvttl display port g5 ch2p_lv_o/g6 100 ao lvds data, shared with lvttl display port g6 ch2n_lv_o/g7 101 ao lvds data, shared with lvttl display port g7 ch1p_lv_o/b0 102 ao lvds data, shared with lvttl display port b0 ch1n_lv_o/b1 103 ao lvds data, shared with lvttl display port b1 ch0p_lv_o/b2 104 ao lvds data, shared with lvttl display port b2 ch0n_lv_o/b3 105 ao lvds data, shared with lvttl display port b3 avss_out_lv 106 ag ground for lvds/ttl outpu ts. tie directly to system ground. avdd_out_lv_3.3 107 ap 3.3v supply for lvds/ttl outputs. bypass to system ground with a 0.1uf capacitor. table 2: 656 video port pad name pin i/o description gpio_24/vda[0] 215 io gpio_24/656 video data[0] [5v-tolerant, internal pull-down] gpio_25/vda[1] 216 io gpio_25/656 video data[1] [5v-tolerant, internal pull-down] gpio_26/vda[2] 217 io gpio_26/656 video data[2] [5v-tolerant, internal pull-down] gpio_27/vda[3] 218 io gpio_27/656 video data[3] [5v-tolerant, internal pull-down] gpio_28/vda[4] 219 io gpio_28/656 video data[4] [5v-tolerant, internal pull-down] gpio_29/vda[5] 220 io gpio_29/656 video data[5] [5v-tolerant, internal pull-down] gpio_30/vda[6] 221 io gpio_30/656 video data[6] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 9 pad name pin i/o description [5v-tolerant, internal pull-down] gpio_31/vda[7] 222 io gpio_31/656 video data[7] [5v-tolerant, internal pull-down] vclk 223 i video port data clock input. [5v-tolerant, internal pull-down] table 3: 16-bit video input pin name no i/o description itu601_4/gpio_36 2 io gpio_36/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_3/gpio_35 3 io gpio_35/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_2/gpio_34 4 io gpio_34/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_1/gpio_33 5 io gpio_33/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_0/gpio_32 6 io gpio_32/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_de 232 i itur-bt601 data enable input [5v-tolerant, internal pull-down] itu601_fld 233 i itur-bt601 field detect inpu t [5v-tolerant, internal pull-down] itu601_clk 234 i itur-bt601 clock input [5v-tolerant, internal pull-down] itu601_hs 237 i itur-bt601 horizontal sync i nput [5v-tolerant, internal pull-down] itu601_vs 238 i itur-bt601 vertical sync i nput [5v-tolerant, internal pull-down] itu601_15/gpio_47 239 io gpio_47/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_14/gpio_46 240 io gpio_48/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_13/gpio_45 248 io gpio_45/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_12/gpio_44 249 io gpio_44/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_11/gpio_43 250 io gpio_43/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_10/gpio_42 251 io gpio_42/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_9/gpio_41 252 io gpio_41/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_8/gpio_40 253 io gpio_40/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_7/gpio_39 254 io gpio_39/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_6/gpio_38 255 io gpio_38/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] itu601_5/gpio_37 256 io gpio_37/ itur-bt601 yuv4:2 :2 input. [5v-tolerant, internal pull-down] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 10 table 4: analog input port pad name pin i/o description vssa_adc 174 ag analog ground. must be directly connected to the system ground. blue2+ 175 ai positive analog input for blue2 channel. vdda_adc_3.3 176 ap analog power (3.3v) for adc analog blocks that are shared by all three channels. includes bandgap reference, master biasing and full sca le adjust. bypass to system ground with a 0.1uf capacitor. sogmcss2 177 ai green2 input for sync-on-green sync ti p clamping. if sync-on-green (sog) or sync-on-y (soy) is not required then sog_mcss pin should be left unconnected. green2+ 178 ai positive analog input for green2 channel. vssa_adc 179 ag analog ground. must be directly connected to the system ground. red2+ 180 ai positive analog input for red2 channel. vssa_adc 181 ag analog ground. must be directly connected to the analog system ground. blue- 182 ai common negative analog input for blue1/blue2 channel. green- 183 ai common negative analog input for green1/green2 channel. red- 184 ai common negative analog input for red1/red2 channel. vssa_adc 185 ag analog ground. must be directly connected to the analog system ground. blue1+ 186 ai positive analog input for blue1 channel. vdda_adc_3.3 187 ap analog power (3.3v) for adc analog blocks that are shared by all three channels. includes bandgap reference, master biasing and full sca le adjust. bypass to system ground with a 0.1uf capacitor. sogmcss1 188 ai green1 input for sync-on-green sync ti p clamping. if sync-on-green (sog) or sync-on-y (soy) is not required then sog_mcss pin should be left unconnected. green1+ 189 ai positive analog input for green1 channel. vdda_adc_3.3 190 ap analog power (3.3v) for adc analog blocks that are shared by all three channels. includes bandgap reference, master biasing and full sca le adjust. bypass to system ground with a 0.1uf capacitor. red1+ 191 ai positive analog input for red1 channel. vssa_adc 192 ag analog ground. must be directly connected to the system ground. vss1_adc 196 ag digital gnd for adc clocking circuit. must be directly connect ed to the system ground. vdd1_adc_1.8 197 ap digital power (1.8v) for adc encoding logi c. bypass to system ground with a 0.1uf capacitor. table 5: analog input hs/vs pad name pin i/o description hsync2 168 i adc input horizontal sync or composite sync [csync2] input channel 2. [input, programmable schmitt trigger, 5v-tolerant] vsync2 169 i adc input vertical sync channel 2. [input, programmable schmitt trigger, 5v-tolerant]] hsync1 172 i adc input horizontal sync or composite sync [cysync1] input1. [input, programmable schmitt trigger, 5v-tolerant] vsync1 173 i adc input vertical sync input channel 1 [input, programmable schmitt trigger, 5v-tolerant]] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 11 table 6: dvi receiver pad name pin i/o description vssa_dvi 129 ag analog gnd for internal biasing circuits . must be connected directly to the system ground. rext 130 ai external termination resistor. a 1%, 250 oh m resistor should be connected from this pin to vdda_dvi_3.3 pin. vdd_dvi_1.8 131 ap vdd (1.8v) for dvi input logic circui ts. bypass to system ground with a 0.1uf capacitor. vssa_dvi 132 ag analog gnd for internal biasing circuits . must be connected directly to the system ground. rx2+ 133 ai dvi input channel 2 positive rx2- 134 ai dvi input channel 2 negative vdda_dvi_3.3 135 ap analog vdd (3.3v) for internal biasing circuits. bypass to system ground with a 0.1uf capacitor. rx1+ 136 ai dvi input channel 1 positive rx1- 137 ai dvi input channel 1 negative vssa_dvi 138 ag analog gnd for dvi receiver. must be connected directly to the system ground. vdd_dvi_1.8 139 ap vdd (1.8v) for dvi input logic circui ts. bypass to system ground with a 0.1uf capacitor. vssa_dvi 140 ag analog gnd for dvi receiver. must be connected directly to the system ground. rx0+ 141 ai dvi input channel 0 positive rx0- 142 ai dvi input channel 0 negative vdda_dvi_3.3 143 ap analog vdd (3.3v) for dvi input analog pll circuits. bypass to system ground with a 0.1uf capacitor. rxc+ 144 ai dvi clock input positive side rxc- 145 ai dvi clock input negative side vss_dvi 146 ag digital gnd for dvi pll. tie directly to system ground. vdd_dvi_1.8 147 ap vdd (1.8v) for dvi input logic circui ts. bypass to system ground with a 0.1uf capacitor. table 7: clocks pad name pin i/o description vbufc_rpll 198 ao analog test pin for clocks, rclk pll, dv i pll and lvds pll. bypass to system ground with a 0.1uf capacitor. vdd_rpll_1.8 199 ap 1.8v digital core power for rclk. bypass to system ground with a 0.1uf capacitor. vss_rpll 200 ag ground for the dds reference pll and digital core. tie directly to system ground. xtal 201 ao crystal oscillator output. tclk and xtal use same pad cell because the pdx003dg oscillator has 2 pads in it tclk 202 ai reference clock (tclk) from the 14.3mhz crystal or ttl oscillator. avdd_rpll_3.3 203 ap analog power (3.3v) for the reference dds pll. bypass to system ground with a 0.1uf capacitor. free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 12 table 8: digital power and ground pad name pin i/o description rvdd_3.3 7 26 35 46 65 114 151 161 167 224 247 p ring vdd, 3.3v. all power pins must be by passed to system ground with a 0.1uf ceramic capacitor placed in close proximity of the pin. cvdd_1.8 30 66 113 123 170 213 235 246 p core vdd, 1.8v. all power pins must be by passed to system ground with a 0.1uf ceramic capacitor placed in close proximity of the pin. crvss 1 14 25 34 47 57 67 73 78 112 124 150 156 162 171 212 225 236 245 g ring/core shared vss. tie directly to the system ground. table 9: system interface pad name pin i/o description ppwr 79 o panel power control. to be used wi th pbias for correct power up/down sequencing (timing is user programm able). [tri-state output] pbias 80 o panel bias control (backlight enable) . to be used with ppwr for correct power up/down sequencing (timing is user programmable). [tri-state output] gpio_10/b4 108 io gpio_10; shared with lvttl disp lay port blue 4; [5v-tolerant, internal pull-down] gpio_11/b5 109 io gpio_11; shared with lvttl disp lay port blue 5; [5v-tolerant, internal pull-down] gpio_12/b6 110 io gpio_12; shared with lvttl disp lay port blue 6; [5v-tolerant, internal pull-down] gpio_13/b7 111 io gpio_13; shared with lvttl disp lay port blue 7; [5v-tolerant, internal pull-down] gpio_14/dclk 115 io gpio_14; shared with lvttl disp lay port dclk; [5v-tolerant, internal pull-down] gpio_15/den 116 io gpio_15; shared with lvttl disp lay port den; [5v-tolerant, internal pull-down] gpio_16/dhs 117 io gpio_16; shared with lvttl display port dhs [5v-tolerant, internal pull-down] gpio_17/dvs 118 io gpio_17; shared with lvttl display port dvs [5v-tolerant, internal pull-down] gpio_18/ scl_0(2w_mst) 119 io gpio_18; shared with two_wire master_0 clock [schmitt trigger, 5v-tolerant] gpio_19/sda_0(2w_mst) 120 io gpio_19; shared with two_wire master_0 data [schmitt trigger, 5v-tolerant] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 13 pad name pin i/o description gpio_20/scl_1(2w_mst) 121 io gpio_20; shared with two_wire master_1 clock [schmitt trigger, 5v-tolerant] gpio_21/sda_1(2w_mst) 122 io gpio_21; shared with two_wire master_1 data [schmitt trigger, open drain, 5v-tolerant] requires external pull up ddc_scl_ch2 148 io ddc2bi channel 2 clock; [schmitt trigger, 5v-tolerant] ddc_sda_ ch2 149 io ddc2bi channel 2 data; [schmitt trigger, 5v-tolerant] ddc_scl_ ch1 152 io ddc2bi channel 1 clock; [schmitt trigger, 5v-tolerant] ddc_sda_ ch1 153 io ddc2bi channel 1 data, [schmitt trigger, 5v-tolerant] uart_di 154 io uart data input [5v-tolerant, internal pull-down] uart_do/boot[3] 155 io uart data ou tput, shared functions: boot[3] [5v-tolerant, internal pull-down] gpio_7/jtag_mode 157 io gpio_7 or jtag boundary scan mode [5v-tolerant, internal pull-up] gpio_6/jtag_clk 158 io gpio_6 or jtag boundary scan clk [5v-tolerant, internal pull-up] gpio_5/jtag_tdi 159 io gpio_5 or jtag boundary scan tdi [5v-tolerant, internal pull-up] gpio_4/jtag_tdo 160 io gpio_4 or jtag boundary scan tdo [5v-tolerant, internal pull-up] gpio_3/jtag_reset 163 io gpio_3 or jtag boundary scan reset [5v-tolerant, internal pull-up] gpio_2 164 io gpio_2 [5v-tolerant, internal pull-down] gpio_49 165 io gpio_49 [open drain 5v-tolerant] requires external pull up gpio_48 166 io gpio_48 [5v-tolerant] resetn 204 io hardware power-on-reset out (active low), and reset button input. reset pulse output of typ. 150ms. gpio_22/int1 211 io gpio_22; shared with interru pt input 1; also shared with interrupt out [5v-tolerant, internal pull-down] gpio_23/int0 214 io gpio_23; s hared with interrupt input 0 [5v-tolerant, internal pull-down] gpio_0/ddc_scl_0 230 io gpio_0/ddc_scl shared with two_wire slave (ddc2b) clock input. [schmitt trigger, 5v-tolerant] gpio_1/ddc_sda_0 231 io gpio_1/ddc_sda shared with two_wire slave (ddc2b) data i/o. [schmitt trigger, 5v-tolerant] pwm0/boot[5] 241 io pwm0; shared with boot[5]; [5v-tolerant, internal pull-down] pwm1/boot[4] 242 io pwm1; shared with boot[4]; [5v-tolerant, internal pull-down] gpo_8/pwm2/boot[6] 243 io gpo_8; shared wi th pwm2 output; shared with boot[6] input. [5v-tolerant, internal pull-down] gpo_9/pwm3/boot[7] 244 io gpo_9/pwm3 [5v-tolerant, internal pull-down] gpo_0 69 o gpo. do not connect when not used gpo_1 70 o gpo. do not connect when not used gpo_2 71 o gpo. do not connect when not used gpo_3 72 o gpo. do not connect when not used gpo_4 74 o gpo. do not connect when not used gpo_5 75 o gpo. do not connect when not used gpo_6 77 o gpo. do not connect when not used gpo_7 126 o gpo. do not connect when not used free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 14 table 10: sdram interface pad name pin i/o description dq7_a 8 io data 7 for first 1mx16 sdram dq6_a 9 io data 6 for first 1mx16 sdram dq5_a 10 io data 5 for first 1mx16 sdram dq4_a 11 io data 4 for first 1mx16 sdram dq3_a 12 io data 3 for first 1mx16 sdram dq2_a 13 io data 2 for first 1mx16 sdram dq1_a 15 io data 1 for first 1mx16 sdram dq0_a 16 io data 0 for first 1mx16 sdram dq15_a 17 io data 15 for first 1mx16 sdram dq14_a 18 io data 14 for first 1mx16 sdram dq13_a 19 io data 13 for first 1mx16 sdram dq12_a 20 io data 12 for first 1mx16 sdram dq11_a 21 io data 11 for first 1mx16 sdram dq10_a 22 io data 10 for first 1mx16 sdram dq9_a 23 io data 9 for first 1mx16 sdram dq8_a 24 io data 8 for first 1mx16 sdram we# 27 o sdram write enable. this signal is active low cas# 28 o sdram column address strobe. this signal is active low ras# 29 o sdram row address strobe. this signal is active low ba 31 o sdram clock enable. this signal is active high mclk 32 o sdram clock. this signal is rising edge active a9 33 io sdram address 9 a8 36 io sdram address 8 a7 37 io sdram address 7 a6 38 io sdram address 6 a5 39 io sdram address 5 a4 40 io sdram address 4 a3 41 io sdram address 3 a2 42 io sdram address 2 a1 43 io sdram address 1 a0 44 io sdram address 0 a10 45 io sdram address 10 dq7_b 48 io data 7 for second 1mx16 sdram dq6_b 49 io data 6 for second 1mx16 sdram dq5_b 50 io data 5 for second 1mx16 sdram dq4_b 51 io data 4 for second 1mx16 sdram dq3_b 52 io data 3 for second 1mx16 sdram dq2_b 53 io data 2 for second 1mx16 sdram dq1_b 54 io data 1 for second 1mx16 sdram dq0_b 55 io data 0 for second 1mx16 sdram dq15_b 56 io data 15 for second 1mx16 sdram dq14_b 58 io data 14 for second 1mx16 sdram dq13_b 59 io data 13 for second 1mx16 sdram dq12_b 60 io data 12 for second 1mx16 sdram dq11_b 61 io data 11 for second 1mx16 sdram dq10_b 62 io data 10 for second 1mx16 sdram dq9_b 63 io data 9 for second 1mx16 sdram dq8_b 64 io data 8 for second 1mx16 sdram free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 15 pad name pin i/o description dqm 68 o sdram data mask table 11: general-purpose lbadc pad name pin i/o description lbadc_rtn/gnd 205 ag analog ground for low bandwidth adc. this package pin is shared with reference feedback pad. tie directly to system ground. lbadc_in3 206 ai analog input 3 to lb-adc analog multiplexer lbadc_in2 207 ai analog input 2 to lb-adc analog multiplexer lbadc_in1 208 ai analog input 1 to lb-adc analog multiplexer lbadc_vdd_3.3 209 ap analog 3.3v supply for low bandwidth-adc. bypass to system ground with a 0.1uf capacitor. table 12: spi rom pin name no i/o description spi_csn/boot[0] 226 io spi rom chip select shared functions: boot[0] spi_clk/boot[1] 227 io spi rom clock output shared functions: boot[1] spi_di 228 io spi rom data input spi_do/boot[2] 229 io spi rom data output shared function: boot[2] table 13: scan test pin name no i/o description scan_en 125 i scan test enable [schmitt trigger with internal pull-down] jtag_bs_en 210 i boundary scan test enable. 0 = no jtag; 1 = enable jtag functions on pins 194, 197-200. [schmitt trigger with internal pull-down] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 16 4 functional description figure 3: functional block diagram 4.1 bootstrap configuration during ? hardware ? reset ? pins ? boot[7..0] ? are ? configured ? as ? inputs. ?? on ? the ? rising ? edge ? of ? resetn, ? the ? value ? on ? these ? pins ? are ? latched ? and ? stored. ?? the ? latched ? values ? configure ? the ? hardware ? to ? certain ? configuration ? without ? any ? software ? interaction. ? these ? values ? are ? software ? readable ? by ? the ? on \ chip ? microcontroller. ?? install ? a ? 10k ? pull \ up ? resistor ? to ? indicate ? a ? ?1?, ? otherwise ? install ? a ? 10k ? pull \ down ? resistor ? to ? indicate ? a ? ?0?. ?? this ? ensures ? correct ? operation ? under ? all ? conditions, ? even ? though ? these ? boot \ strap ? pins ? have ? internal ? 60k ? pull \ downs. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 17 table 14: bootstrap signals pin pin name, signal name i/o shared with description 226 boot[0], ocm_bus_sel[0] i spi_csn interface select. determines the interf ace to control this device and configures jtag access 00 = internal micro, spi as rom. internal rom on, and mapped to top 32k of ocm address range. ocm boot will be from internal rom code. (recommended) 01 = internal micro, internal rom is overlayed with external rom. internal rom off. this is debug mode with the external rom mapped to the entire upper 512k of the ocm address range. ocm boot will be from external rom code. 10, 11 = reserved for factory testing 227 boot[1], ocm_bus_sel[1] i spi_clk see ocm_bus_sel[0] 229 boot[2], osc_sel i spi_do selection of tclk source 0 = xtal and internal oscillator (recommended) 1 = ttl oscillator (input on tclk pin) 155 boot[3], icd_sel i uart_do 0 = in circuit debugger is mapped onto the ddc_scl_ch2 and ddc_sda_ch2 pins. 1 = in circuit debugger is mapped onto the ddc_scl_ch1 and ddc_sda_ch1 pins. 242 boot[4], ocm_24bit_addr_en i pwm1 0 = ocm is booting in 20 bit addressing mode. 1 = ocm is booting in 24 bit addressing mode. 241 boot[5], tclk_sel[0] i pwm0 checked by internal rom firmware to select tclk frequency. see boot[7] below. 243 boot[6], atmel_en i gpo_8/pwm2 0 ? standard spi external memory interface; 1 ? atmel data flash external memory interface. 244 boot[7], tclk_sel[1] i gpo_9/pwm3 checked by internal rom firmware to select tclk frequency. tclk_sel[1:0] = tclk frequency 00 = 14.318 mhz; 01 = 20 mhz; 10 = 24 mhz; 11 = 19.661 mhz ? ? ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 18 4.2 chip initialization 4.2.1 power sequencing at ? any ? time ? during ? the ? power \ up ? sequence ? the ? actual ? voltage ? of ? the ? ring ? power ? supply ? (rvdd_3.3) ? should ? always ? be ? equal ? to ? or ? higher ? than ? the ? actual ? voltage ? of ? the ? core ? power ? supply ? (cvdd_1.8). ?? in ? mathematical ? terms, ? v rvdd_3.3 ? >= ? v cvdd_1.8 ? at ? all ? times. ?? in ? addition, ? the ? system ? designer ? must ? ensure ? that ? the ? 1.8v ? core ? vdd ? supply ? must ? be ? active ? for ? at ? least ? 1ms ? before ? the ? rising ? edge ? of ? the ? chip ? resetn ? signal ? during ? the ? chip ? power \ up ? sequence. ? the ? rising ? edge ? of ? resetn ? signal ? is ? used ? to ? latch ? the ? bootstrap ? configurations, ? so ? its ? correct ? timing ? relationship ? to ? the ? core ? vdd ? is ? critical ? for ? correct ? chip ? operation. ? table 15: power sequencing requirements parameter min typ max vrvdd-cvdd(for all t>0) 0v tcvdd->resetn 100ms figure 4: correct power sequencing rvdd_ 3.3 cvdd_1.8 time voltage v rvdd-cvdd (t) resetn time voltage 0v t cvdd->resetn t ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 19 4.2.2 hardware reset this ? device ? has ? an ? integrated ? internal ? reset ? pulse ? generator, ? so ? that ? an ? external ? reset ? ic ? is ? not ? required. ? the ? internal ? circuitry ? of ? the ? reset ? is ? shown ? below. ? figure 5: internal reset circuitry reset logic resetn control logic with brown-out protection ref. voltage genesis device r2 vdd optional r1 +3.3v the ? internal ? reset ? pulse ? generator ? performs ? hardware ? reset ? under ? the ? following ? conditions: ? ? during ? system ? power \ up, ? after ? the ? rvdd_3.3 ? voltage ? has ? reached ? threshold ? vt. ? ? in ? the ? event ? rvdd_3.3 ? voltage ? drops ? below ? threshold ? vt ? for ? more ? than ? approximately ? 200ns. ? ? manually ? holding ? the ? resetn ? pin ? low ? for ? a ? minimum ? of ? 1ms. ? the ? active \ low ? reset ? pulse ? on ? resetn ? pin ? generated ? by ? the ? internal ? reset ? pulse ? generator ? is ? around ? 100ms ? in ? duration. ?? tclk ? input ? must ? be ? applied ? during ? and ? after ? the ? reset. ?? when ? the ? reset ? period ? is ? complete, ? and ? resetn ? state ? becomes ? high, ? and ? the ? reset ? sequence ? is ? as ? follows: ? 1. reset all registers of all types to their default state (this is 00h unless otherwise specified in the register listing). ? 2. force each clock domain into reset. this c ontinues for 64 local clock domain cycles following the de-assertion of resetn. ? 3. operate the ocm_clk domain at the tclk frequency. ? the ? following ? figure ? shows ? the ? relationship ? between ? avdd_3.3v ? and ? resetn ? during ? system ? power \ up. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 20 figure 6: power-up reset sequence between rvdd_3.3 and resetn pin t t rvdd_3.3 3.3v vt resetn 3.3v t r t p push button hold time t r note: ? vt ? is ? the ? power \ up ? reset ? threshold ? voltage, ? tr ? is ? the ? reset ? pulse ? duration, ? and ? tp ? is ? the ? push \ button ? hold ? time ? (the ? duration ? of ? holding ? resetn ? pin ? low). ? the ? power \ on ? reset ? specifications ? are ? listed ? in ? the ? following ? table. ? table 16: power-on reset specification description symbol min. typical max power-on reset threshold vo ltage vt 2.10v 2.20v 2.40v reset pulse duration tr 80ms 100ms 120ms push-button hold time tp 1ms there ? is ? a ? glitch ? filter ? in ? the ? internal ? reset ? pulse ? generator ? that ? ignores ? the ? rvdd_3.3 ? power ? line ? glitch ? if ? the ? glitch ? duration ? is ? shorter ? than ? approximately ? 200ns, ? regardless ? of ? the ? magnitude ? of ? the ? glitch. ?? however, ? if ?? rvdd_3.3v ? voltage ? drops ? below ? the ? threshold ? vt ? for ? more ? than ? 200ns, ? reset ? will ? be ? asserted: ? resetn ? will ? become ? low. ?? the ? following ? figure ? illustrates ? the ? rvdd_3.3v ? glitch. ? figure 7: reset power supply glitch td vg vt 0 3.3v t avdd_rpll_3.3 ? td ? = ? duration ? of ? dip ? glitch ? at ? v t ? vg ? = ? amplitude ? of ? dip ? glitch ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 21 table 17: rvdd_3.3v glitch-i nduced reset specifications description symbol min. typical max rvdd_3.3v glitch duration td 200ns rvdd_3.3v glitch amplitude vg 0.9v* 1.2v* ? * ? the ? rvdd_3.3v ? voltage ? must ? fall ? by ? more ? than ? vg ? below ? the ? supply ? voltage ? (3.3v ? nominal) ? for ? the ? reset ? to ? assert ? (resetn ? becomes ? low). ?? for ? example, ? rvdd_3.3v ? voltage ? level ? must ? fall ? below ? at ? least ? 2.4v ? (3.3v ? ? ? 0.9v) ? in ? order ? for ? reset ? to ? assert. ? 4.3 clock generation this ? device ? is ? designed ? to ? use ? a ? single ? crystal. ? all ? internal ? clocks ? required ? for ? the ? operation ? of ? the ? chip ? are ? generated ? internally ? using ? analog ? and ? digital ? pll?s ? . ? the ? pll?s ? use ? tclk ? as ? a ? reference ? frequency. ?? tclk ? is ? generated ? using ? an ? external ? crystal ? with ? the ? chip?s ? internal ? oscillator. ? 4.3.1 using the internal osc illator with external crystal the ? oscillator ? circuit ? is ? designed ? to ? provide ? a ? very ? low ? jitter ? and ? very ? low ? harmonic ? clock ? to ? the ? internal ? circuitry ? of ? the ? chip. ? an ? automatic ? gain ? control ? (agc) ? circuit ? is ? used ? to ? insure ? startup ? and ? operation ? over ? a ? wide ? range ? of ? conditions. ? the ? oscillator ? circuit ? also ? minimizes ? the ? overdrive ? of ? the ? crystal ? to ? reduce ? the ? aging ? of ? the ? crystal. ? when ? the ? internal ? oscillator ? is ? enabled ? a ? crystal ? resonator ? is ? connected ? between ? tclk ? and ? the ? xtal ? with ? the ? appropriately ? sized ? loading ? capacitors ? c l1 ? and ? c l2 . ? the ? size ? of ? c l1 ? and ? c l2 ? are ? determined ? from ? the ? crystal ? manufacturer?s ? specification ? and ? by ? compensating ? for ? the ? parasitic ? capacitance ? of ? the ? genesis ? device ? and ? the ? printed ? circuit ? board ? traces. ? the ? loading ? capacitors ? are ? terminated ? to ? the ? analog ? vdd ? power ? supply. ? this ? connection ? increases ? the ? power ? supply ? rejection ? ratio ? when ? compared ? to ? terminating ? the ? loading ? capacitors ? to ? ground, ? thus ? minimizing ? tclk ? jitter. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 22 figure 8: using the internal o scillator with external crystal reset state logic n/c xtal tclk osc_out tclk distribution internal pull down genesis device vdd 180 ua 100 k cl1 cl2 internal oscillator e nable vdda vdda bootstrap 60k the ? tclk ? oscillator ? uses ? a ? pierce ? oscillator ? circuit. ? the ? output ? of ? the ? oscillator ? circuit, ? measured ? at ? the ? tclk ? pin, ? is ? an ? approximate ? sine ? wave ? with ? a ? bias ? of ? about ? 2 ? volts ? above ? ground. ? the ? output ? of ? the ? oscillator ? is ? connected ? to ? a ? comparator ? that ? converts ? the ? sine ? wave ? to ? a ? square ? wave. ? the ? comparator ? requires ? a ? minimum ? signal ? level ? of ? about ? 50 \ mv ? peak ? to ? peak ? to ? function ? correctly. ? the ? output ? of ? the ? comparator ? is ? buffered ? and ? then ? distributed ? to ? the ? internal ? circuits. ? figure 9: internal oscillator output ~ 2.5 volts time ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 23 4.3.2 clock synthesis all ? internal ? clocks ? required ? for ? proper ? chip ? operation ? are ? synthesized ? internally ? within ? the ? GM5862H. ? 1. main ? timing ? clock ? (tclk) ? is ? the ? output ? of ? the ? chip ? internal ? crystal ? oscillator. ? tclk ? is ? derived ? from ? the ? tclk/xtal ? pad ? input. ?? max ? = ? 24mhz ? 2. reference ? clock ? (rclk) ? synthesized ? by ? rclk ? pll ? using ? tclk ? or ? extclk ? as ? the ? reference. ?? this ? clock ? is ? used ? as ? a ? reference ? clock ? in ? generating ? most ? of ? the ? internal ? frequencies. ?? it ? is ? important ? that ? this ? clock ? is ? stable ? with ? very ? low ? jitter. ? factory ? recommended ? frequency ? is ? 200mhz. ? 3. input ? source ? clock ? (sdds_clk) ? synthesized ? by ? sdds ? pll ? using ? input ? hs ? as ? the ? reference. ? the ? sdds ? uses ? rclk ? as ? a ? reference ? clock ? to ? drive ? its ? internal ? digital ? logic. ? max ? = ? 195mhz. ? 4. dvi ? output ? clock ? (dvi_clk) ? synthesized ? by ? dvi ? receiver ? pll ? using ? rc+/rc \ as ? the ? reference. ? dvi ? clock ? max ? = ? half ? 165 ? mhz. ? 5. digital ? input ? clock ? domain ? for ? itu656 ? video ? input ? (dip_clk). ? max ? = ? 80mhz ? 6. digital ? input ? clock ? domain ? for ? itu601 ? input ? (itu601_clk). ? single ? edged ? maximum ? = ? 74.25mhz ? and ? dual ? edge ? maximum ? = ? 148.5mhz ? 7. fixed ? frequency ? clock ? (fclk) ? synthesized ? by ? fdds. ? used ? as ? host ? interface ? and ? on \ chip ? micro \ controller ? clock ? (ocm_clk). ?? max ? = ? 100mhz ? 8. memory ? clock ? synthesized ? by ? mdds. ?? used ? as ? memc_clk ? domain ? driver. ?? also ? typically ? drives ? the ? lbuf_clk. ? max ? = ? 187 ? mhz. ? 9. display ? clock ? (ddds_clk) ? synthesized ? by ? ddds ? pll ? using ? imp_clk ? as ? the ? reference. ? the ? imp_clk ? is ? the ? clock ? from ? the ? selected ? main ? channel ? video ? source. ?? the ? ddds ? also ? uses ? the ? rclk ? to ? drive ? internal ? digital ? logic. ? 4.4 analog input port (aip) the ? aip ? support ? dual ? analog ? inputs ? with ? separate ? sets ? of ? hsync, ? vsync ? and ? composite/sog ? inputs. ? an ? integrated ? mux ? selects ? which ? set ? of ? analog ? inputs ? connect ? to ? the ? integrated ? adc. ? analog ? front ? end ? is ? responsible ? for ? selecting ? and ? capturing ? the ? desired ? analog ? input ? graphics/video ? stream. ? the ? adc ? can ? be ? used ? to ? sample ? analog ? signals ? in ? rgb ? as ? well ? as ? the ? ypbpr ? color ? space, ? in ? which ? case ? the ? digital ? color ? controls ? are ? used ? to ? convert ? these ? signals ? back ? to ? the ? rgb ? color ? domain ? for ? display ? on ? the ? lcd ? panel. ? when ? a ? source ? is ? a ? video ? input ? stream ? (ypbpr) ? the ? aip ? directs ? inputs ? through ? an ? analog ? multiplexer ? to ? integrated ? anti \ alias ? filters ? before ? the ? analog ? to ? digital ? conversion ? (adcs). ? these ? integrated ? features ? eliminate ? the ? need ? for ? any ? external ? devices ? (anti \ alias \ filters, ? analog ? multiplexers) ? between ? the ? input ? connector ? and ? the ? analog ? input ? port. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 24 the ? aip ? block ? also ? contains ? the ? sync ? processor ? block ? which ? processes ? digital ? separate ? and ? digital ? composite ? syncs. ? for ? processing ? sog/soy ? signals ? the ? analog ? sync ? extractor, ? within ? the ? adc ? block ? is ? utilized. ? the ? vbi ? section ? of ? the ? aip ? block ? extracts ? and ? decodes ? the ? vbi ? data ? from ? the ? analog ? data ? stream. ? this ? data ? is ? sent ? to ? the ? internal ? on \ chip ? microcontroller ? for ? further ? processing. ? 4.4.1 analog to digital converter (adc) the ? following ? section ? describes ? analog ? rgb ? signal ? connections. ? table 18: pin connection fo r rgb input with hsync/vsync pin name adc signal name red1+ red/pr channel 1 red2+ red/pr channel 2 green1+ green/y channel 1 green2+ green/y channel 2 blue1+ blue/pb channel 1 blue2+ blue/pb channel 2 red- terminate as illustrated in the figure below. green- terminate as illustrated in the figure below. blue- terminate as illustrated in the figure below. hsync horizontal sync. terminate as illustrated in the figure below. vsync vertical sync. terminate as with hsync illustrated in the figure below. free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 25 figure 10: example adc signal terminations db15 red gnd green blue hsync vsync pr y pb hs2 hsync vs2 vsync hs1 75 75 75 75 75 75 r2+ g2+ b2+ r1+ g1+ b1+ 0.01uf 0.01uf 0.01uf 0.01uf 0.01uf 0.01uf 0.01uf 10k r1 r2 r3 r4 r5 r6 vs1 10k genesis device r- r7 g- r8 b- r9 0.01uf 0.01uf ? it ? is ? important ? to ? follow ? the ? recommended ? layout ? guidelines ? for ? graphics ? signal ? interfacing ? from ? compatible ? sources ? (see ? the ? system ? layout ? guidelines). ? 4.4.2 schmitt trigger integrated ? schmitt ? triggers ? are ? used ? for ? improving ? the ? rising ? and ? falling ? edges ? of ? the ? analog ? horizontal ? and ? vertical ? sync ? signals. ? this ? eliminates ? the ? need ? for ? using ? external ? schmitt ? components ? in ? the ? system ? design. ? typical ? behavior ? of ? an ? integrated ? schmitt ? circuit ? is ? shown ? in ? the ? following ? figure. ? the ? integrated ? schmitt ? circuit ? has ? 2 ? sets ? of ? threshold ? voltages ? for ? vih ? and ? vil, ? which ? together ? allows ? four ? different ? hysteresis ? levels. ? the ? schmitt ? threshold ? levels ? of ? integrated ? circuits ? are ? in ? compliance ? with ? standard ? cmos ? and ? ttl ? input ? signals. ? a ? programmable ? option ? is ? provided ? in ? the ? software ? for ? the ? selection ? of ? schmitt ? levels. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 26 figure 11: schmitt circuit timing diagram input to schmitt trigger schmitt trigger output v ih v il hysteresis = v ih - v il ? table 19: schmitt circuit thresholds description programmed threshold level static thresholds (measured with a dc voltage) dynamic thresholds (10khz triangular waveform) min typ max min typ max low-to-high vih[v] = 2.5 2.16 2.5 2.64 2.06 2.34 2.62 vih[v] = 2.0 1.82 1.99 2.16 1.72 1.92 2.1 high-to-low vil [v] = 1.5 1.3 1.5 1.84 1.1 1.36 1.58 vil [v] = 0.8 0.74 0.8 0.91 0.52 0.6 0.73 ? 4.4.3 dc restoration the ? various ? analog ? inputs ? generated ? from ? different ? graphics ? sources ? may ? have ? dc ? offsets. ? it ? is ? necessary ? to ? remove ? the ? dc ? offsets ? by ? ac ? coupling ? these ? signals ? through ? capacitive ? filters ? as ? recommended ? in ? the ? earlier ? diagram. ? analog ? front ? end ? provides ? means ? to ? remove ? dc ? offsets ? so ? that ? the ? entire ? dynamic ? range ? of ? the ? adc ? can ? be ? fully ? utilized. ? typically, ? this ? is ? achieved ? by ? clamping ? the ? input ? signal ? during ? the ? horizontal ? back ? porch ? region. ? full ? control ? over ? any ? such ? clamping ? pulse ? is ? provided ? so ? that ? the ? position ? and ? size ? can ? be ? controlled ? via ? programmable ? registers. ??? 4.4.4 sync extraction the ? composite ? sync ? pattern ? may ? be ? input ? on ? either ? the ? hsync ? input ? pin ? or ? be ? embedded ? into ? green ? channel. ? an ? internal ? sync ? stripper ? is ? responsible ? for ? extracting ? composite ? sync ? signals ? or ? sog ? signals. ?? input ? measurement ? circuitry ? is ? used ? to ? determine ? the ? polarity ? and ? whether ? the ? sync ? signals ? are ? separate ? hsync ? / ? vsync, ? composite ? sync ? or ? sync \ on \ green. ? this ? device ? has ? the ? capability ? to ? support ? the ? following ? types ? of ? sog ? and ? csync ? inputs ? without ? having ? to ? use ? external ? components. ? the ? signals ? below ? show ? the ? negative ? types ? of ? sog ? and ? csync ? signals ? (positive ? types ? are ? also ? supported). ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 27 4.4.5 adc characteristics table 20: adc characteristics min typ max note track & hold amp bandwidth 290 mhz guaranteed by design. note that the track & hold amp bandwidth is programmable. 290 mhz is the maximum setting. full scale adjust range at rgb inputs 0.55 v 0.90 v full scale adjust sensitivity +/- 1 lsb measured at adc output. independent of full scale rgb input. zero scale adjust sensitivity +/- 1 lsb measured at adc output. sampling frequency (fs) 13.5 mhz 205 mhz differential non-linearity (dnl) +/-0.5 lsb +/-0.9 lsb fs = 205 mhz no missing codes guaranteed by test. integral non-linearity (inl) +/- 1.5 lsb fs = 205 mhz channel to channel matching +/- 0.5 lsb input ? formats ? with ? resolutions ? or ? refresh ? rates ? higher ? than ? that ? supported ? by ? the ? lcd ? panel ? are ? displayed ? as ? recovery ? modes ? only. ? this ? is ? called ? realrecovery?. ? for ? example, ? it ? may ? be ? necessary ? to ? shrink ? the ? image. ? this ? may ? introduce ? image ? artifacts. ? however, ? the ? image ? is ? clear ? enough ? to ? allow ? the ? user ? to ? change ? the ? display ? properties. ? the ? adc ? has ? a ? built ? in ? clamp ? circuit ? for ? ac \ coupled ? inputs. ? by ? inserting ? series ? capacitors ? (~10 ? nf), ? the ? dc ? offset ? of ? an ? external ? video ? source ? can ? be ? removed. ? the ? clamp ? pulse ? position ? and ? width ? are ? programmable. ? 4.4.6 clock recovery circuit the ? source ? direct ? digital ? synthesis ? (sdds) ? clock ? recovery ? circuit ? generates ? the ? clock ? used ? to ? sample ? analog ? rgb ? data ? (ip_clk ? or ? source ? clock). ?? this ? circuit ? is ? locked ? to ? the ? hsync ? of ? the ? incoming ? video ? signal. ??? patented ? digital ? clock ? synthesis ? technology ? makes ? the ? clock ? circuits ? resistant ? to ? temperature/voltage ? drift. ? using ? direct ? digital ? synthesis ? (dds) ? technology, ? the ? clock ? recovery ? circuit ? can ? generate ? any ? ip_clk ? clock ? frequency ? within ? the ? range ? of ? 25mhz ? to ? 205mhz. ? figure 12: clock recovery sog sync extractor window capture adc r b hsync (separate or composite) ipclk hsync 24 green analog signal image phase measurement composite phase delay: a_clk sdds free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 28 4.4.7 sampling phase adjustment the ? programmable ? adc ? sampling ? phase ? is ? adjusted ? by ? delaying ? the ? sdds ? clock ? with ? respect ? to ? the ? hsync ? input. ? the ? accuracy ? of ? the ? sampling ? phase ? is ? checked ? and ? the ? result ? is ? read ? from ? a ? register. ? this ? feature ? enables ? accurate ? auto \ adjustment ? of ? the ? adc ? sampling ? phase. ? 4.4.8 adc capture window the ? capture ? window ? is ? defined ? by ? ip_clks ? (equivalent ? to ? a ? pixel ? count) ? in ? the ? horizontal ? direction, ? and ? defined ? by ? lines ? in ? the ? vertical ? direction. ? all ? parameters ? beginning ? with ? ?source? ? are ? programmed ? registers ? values. ?? note: ? the ? input ? vertical ? total ? is ? determined ? solely ? by ? the ? input ? and ? is ? not ? a ? programmable ? parameter. ? figure 13: adc capture window capture window source width source hstart source horizontal total (pixels) source vstart source height input vertical total (lines) reference point the ? reference ? point ? in ? the ? adc ? capture ? window ? figure ? marks ? the ? leading ? edge ? of ? the ? first ? internal ? hsync ? following ? the ? leading ? edge ? of ? an ? internal ? vsync. ? both ? the ? internal ? hsync ? and ? the ? internal ? vsync ? are ? derived ? from ? external ? hsync ? and ? vsync ? inputs. ? horizontal ? parameters ? are ? defined ? in ? terms ? of ? single ? pixel ? increments ? relative ? to ? the ? internal ? horizontal ? sync. ? vertical ? parameters ? are ? defined ? in ? terms ? of ? single ? line ? increments ? relative ? to ? the ? internal ? vertical ? sync. ? adc ? interlaced ? inputs ? may ? be ? programmed ? to ? automatically ? determine ? the ? field ? type ? (even ? or ? odd) ? from ? the ? vsync/hsync ? relative ? timing. ? for ? more ? information ? see ? the ? input ? format ? measurement ? section. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 29 4.5 digital visual interface (dvi) input port the ? ultra \ reliable ? dvi? ? receiver ? block ? is ? compliant ? with ? dvi ? 1.0 ? single ? link ? specifications. ? digital ? visual ? interface ? (dvi) ? is ? a ? standard. ?? this ? block ? supports ? an ? input ? clock ? frequency ? ranging ? from ? 20 ? mhz ? to ? 165 ? mhz. ? 4.5.1 dvi receiver characteristics table 21: dvi receiver characteristics min typ max note dc characteristics differential input voltage 150mv 1200mv input common mode voltage avdd ?300m v avdd -37mv behavior when transmitter disable avdd -10mv avdd +10mv ac characteristics input clock frequency 20 mhz 165 mhz input differential sensitivity (peak-to-peak) 150mv max differential input (pea k-to-peak) 1560 mv allowable intra-pair skew at receiver 250 ps allowable inter-pair skew at receiver 4.0 ns input clock = 160 mhz ? it ? is ? important ? to ? follow ? the ? recommended ? layout ? guidelines ? for ? these ? signals. ? ? 4.5.2 high-bandwidth digita l content protection (hdcp) the ? hdcp ? system ? allows ? authentication ? of ? a ? video ? receiver ? by ? a ? video ? transmitter, ? decryption ? of ? transmitter \ encoded ? video ? data ? by ? the ? receiver, ? and ? periodic ? renew \ ability ? of ? authentication ? during ? transmission. ?? the ? circuitry ? is ? implemented ? to ? allow ? full ? support ? of ? the ? hdcp ? 1.0 ? protocol ? for ? dvi ? inputs. ? for ? enhanced ? security, ? genesis ? provides ? a ? means ? of ? storing ? and ? accessing ? the ? secret ? key ? given ? to ? individual ? monitor ? units ? in ? an ? encrypted ? format. ? further ? details ? of ? the ? protocol ? and ? theory ? of ? the ? system ? can ? be ? found ? in ? the ? high \ bandwidth ? digital ? content ? protection ? system ? specification ? (see ? www.digital-cp.com) . ? 4.6 video input port for itu656 sources (vip) the ? digital ? input ? port ? supports ? itu656 ? digital ? video ? format. ? the ? vip ? connects ? to ? commercially ? available ? ntsc ? or ? pal ? video ? decoders. ? itu \ bt656 ? video ? format ? consists ? of ? pixel ? clock ? and ? 8 \ bits ? of ? data. ?? the ? vip ? port ? allows ? for ? msb ? ? ? lsb ? data ? swapping ? to ? facilitate ? interfacing ? to ? a ? variety ? of ? external ? video ? decoders. ? it ? has ? also ? a ? built ? in ? programmable ? clock ? delay ? circuitry ? to ? compensate ? for ? timing ? skew ? between ? the ? video ? clock ? and ? the ? data, ? which ? would ? otherwise ? cause ? undesirable ? noise ? on ? the ? screen. ? no ? separate ? hsync, ? vsync ? signals ? are ? required. ? the ? internal ? 656 ? decoder ? extracts ? these ? from ? the ? embedded ? timing ? data ? as ? shown ? below. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 30 figure 14: itu-r bt656 input vclk yuv(7:0) (input) y 00 00 ff sav cb y cr y cb 1 1715 1714 1713 0 3 25 4 1712 preamble timing reference word sav (start of active vi deo) active video 1711 1710 blanking y cr cb 00 00 ff eav blanking 1437 1438 1439 1440 1441 1442 1443 preamble timing reference word eav (end of active vi deo) 1444 ycbcr ? input ? is ? always ? automatically ? clamped ? to ? restrict ? the ? input ? data ? to ? itu \ r ? bt601 ? levels: ? ? y ? bottom ? clamping: ?? y ? data ? < ? 16 ? is ? clamped ? to ? 16 ? ? y ? top ? clamping: ?? ? y ? data ? >235 ? is ? clamped ? to ? 235 ? ? cbcr ? bottom ? clamping: ?? cbcr ? data ? < ? 16 ? is ? clamped ? to ? 16 ? ? cbcr ? top ? clamping: ?? cbcr ? data ? > ? 240 ? is ? clamped ? to ? 240 ? 4.7 16-bit ttl input this ? ttl ? input ? supports ? 16 \ bit ? 4:2:2 ? ycbcr ? or ? ypbpr ? format. ? figure 15: 8-bit 4:2:2 ycbcr/ypbpr ? figure 16: 16-bit 4:2:2 ycbcr/ypbpr ? ? 4.8 test pattern generator (tpg) once ? programmed, ? the ? integrated ? test ? pattern ? generator ? can ? replace ? a ? video ? source ? (e.g. ? a ? pc) ? during ? factory ? calibration ? and ? test. ? this ? simplifies ? the ? test ? procedure ? and ? eliminates ? the ? possibility ? of ? image ? noise ? being ? injected ? into ? the ? system ? from ? the ? source. ? foreground ? and ? background ? colors ? are ? programmable, ? and ? the ? osd ? controller ? can ? be ? used ? to ? produce ? other ? patterns. ? it ? can ? be ? also ? used ? as ? a ? diagnostic ? tool ? during ? product ? development. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 31 each ? input ? block ? is ? equipped ? with ? its ? own ? tpg. ? the ? tpg ? within ? the ? analog ? input ? block ? (aip) ? can ? operate ? in ? free \ run ? stand ? alone ? mode ? without ? any ? external ? source ? connected. ? the ? dvi ? and ? the ? vip ? ports ? require ? a ? source ? with ? a ? valid ? timing ? to ? be ? connected. ? the ? timing ? of ? the ? input ? source ? is ? used ? for ? correct ? output ? timing ? generation, ? while ? displaying ? the ? selected ? test ? pattern. ? figure 17: built-in test pattern examples 4.9 input format measurement input ? format ? measurement ? (ifm) ? is ? provided ? on ? both ? main ? and ? pip ? channels. ? the ? ifm ? block ? provides ? the ? capability ? of ? measuring ? the ? horizontal ? and ? vertical ? timing ? parameters ? of ? the ? input ? video ? source ? (hs/vs ? period, ? pulse ? duration, ? polarity, ? number ? of ? vertical ? lines ? within ? the ? input ? field/frame ? etc.). ? this ? information ? is ? used ? to ? determine ? the ? input ? graphics/video ? format ? and ? to ? detect ? any ? changes ? in ? the ? input ? format, ? therefore ? facilitating ? mode ? setup. ?? it ? is ? also ? capable ? of ? detecting ? the ? field ? type ? of ? interlaced ? video ? formats. ? horizontal ? measurements ? are ? measured ? in ? terms ? of ? the ? selected ? ifm_clk ? (either ? tclk ? or ? rclk/4), ? while ? vertical ? measurements ? are ? measured ? in ? terms ? of ? hsync ? pulses ? (number ? of ? lines). ?? the ? ifm ? features ? a ? programmable ? reset, ? separate ? from ? the ? regular ? soft ? reset. ?? this ? reset ? disables ? the ? ifm, ? reducing ? power ? consumption. ? the ? ifm ? is ? capable ? of ? operating ? during ? power ? down ? mode. ?? 4.10 hsync / vsync delay the ? active ? input ? region ? captured ? is ? specified ? with ? respect ? to ? internal ? hsync ? and ? vsync. ? by ? default, ? internal ? syncs ? are ? equivalent ? to ? the ? hsync ? and ? vsync ? at ? the ? input ? pins ? and ? thus ? force ? the ? captured ? region ? to ? be ? bounded ? by ? external ? hsync ? and ? vsync ? timing. ?? however, ? an ? internal ? hsync ? and ? vsync ? delay ? feature ? removes ? this ? limitation. ? the ? hsync ? and ? vsync ? delay ? is ? used ? for ? image ? positioning ? of ? adc ? input ? data. ? hsync ? is ? delayed ? by ? a ? programmed ? number ? of ? selected ? input ? clocks, ? while ? the ? vsync ? is ? delayed ? by ? a ? programmed ? number ? of ? selected ? input ? lines. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 32 figure 18: active data crosses hsync boundary delayed hs placed safely within blanking active data crosses hs boundary data hs (system) internal delayed hs 4.11 horizontal and vertical measurement the ? ifm ? is ? able ? to ? measure ? the ? horizontal ? period ? and ? active ? high ? pulse ? width ? of ? the ? hsync ? signal, ? in ? terms ? of ? the ? selected ? clock ? period ? (either ? tclk ? or ? rclk/4.). ? horizontal ? measurements ? are ? performed ? on ? only ? a ? single ? line ? per ? frame ? (or ? field). ?? the ? line ? used ? is ? programmable. ?? it ? is ? able ? to ? measure ? the ? vertical ? period ? and ? vsync ? pulse ? width ? in ? terms ? of ? rising ? edges ? of ? hsync. ? once ? enabled, ? measurement ? begins ? on ? the ? rising ? vsync ? and ? is ? completed ? on ? the ? following ? rising ? vsync. ? measurements ? are ? made ? on ? every ? field ? / ? frame ? until ? disabled. ? 4.12 format change detection the ? ifm ? is ? able ? to ? detect ? changes ? in ? the ? input ? format ? relative ? to ? the ? last ? measurement ? and ? then ? alert ? both ? the ? system ? and ? the ? on \ chip ? microcontroller. ?? the ? microcontroller ? sets ? a ? measurement ? difference ? threshold ? separately ? for ? horizontal ? and ? vertical ? timing. ?? if ? the ? current ? field ? / ? frame ? timing ? is ? different ? from ? the ? previously ? captured ? measurement ? by ? an ? amount ? exceeding ? this ? threshold, ? a ? status ? bit ? is ? set. ? an ? interrupt ? can ? also ? be ? programmed ? to ? occur. ? 4.13 ifm watchdog the ? watchdog ? monitors ? input ? vsync ? and ? hsync. ? when ? any ? hsync ? period ? exceeds ? the ? programmed ? timing ? threshold ? (in ? terms ? of ? the ? selected ? ifm_clk), ? the ? counter ? times ? out ? indicating ? loss ? of ? sync. ? when ? any ? vsync ? period ? exceeds ? the ? programmed ? timing ? threshold ? (in ? terms ? of ? hsync ? pulses), ? the ? vsync ? watchdog ? counter ? times ? out ? indicating ? loss ? of ? sync. ? both ? of ? these ? events ? set ? individual ? register ? bits. ? the ? time \ out ? status ? can ? be ? read ? by ? the ? ocm, ? or ? an ? interrupt ? can ? also ? be ? programmed ? to ? occur ? under ? this ? condition. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 33 4.14 internal odd/ even field detection the ? ifm ? has ? the ? ability ? to ? perform ? field ? decoding ? of ? interlaced ? inputs ? to ? the ? adc. ? the ? user ? specifies ? start ? and ? end ? values ? to ? outline ? a ? ?window? ? relative ? to ? hsync. ?? if ? the ? vsync ? leading ? edge ? occurs ? within ? this ? window, ? the ? ifm ? signals ? the ? start ? of ? an ? odd ? field. ?? if ? the ? vsync ? leading ? edge ? occurs ? outside ? this ? window, ? an ? even ? field ? is ? indicated ? (the ? interpretation ? of ? odd ? and ? even ? can ? be ? reversed). ?? the ? window ? start ? and ? end ? points ? are ? selected ? from ? a ? predefined ? set ? of ? values. ??? figure 19: odd/even field detection hs window vs - even vs - odd window start window end 4.15 input pixel measurement pixel ? measurement ? functions ? are ? provided ? to ? assist ? in ? configuring ? system ? parameters ? such ? as ? pixel ? clock, ? sdds ? sample ? clocks ? per ? line ? and ? phase ? setting, ? centering ? the ? image, ? or ? adjusting ? the ? contrast ? and ? brightness. ? 4.16 image boundary detection image ? boundary ? detection ? is ? used ? when ? programming ? the ? active ? window ? and ? centering ? the ? image. ? functions ? perform ? measurements ? on ? the ? incoming ? data ? to ? determine ? the ? image ? boundary. ? this ? information ? is ? then ? used ? for ? correctly ? positioning ? the ? image ? on ? the ? display. ? 4.17 image auto balance image ? auto ? balance ? functions ? perform ? min ? and ? max ? pixel ? value ? measurements ? on ? the ? input ? data ? that ? is ? used ? to ? set ? up ? the ? adc ? for ? maximum ? dynamic ? luminance ? range, ? while ? ensuring ? that ? gray ? scales ? are ? properly ? displayed ? on ? the ? display, ? without ? white \ clipping. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 34 4.18 instant auto? instant ? auto ? (patent \ pending) ? is ? a ? new ? auto ? image ? adjustment ? technology ? from ? genesis ? microchip. ? it ? automatically ? configures ? frequency ? and ? phase ? based ? on ? the ? features ? of ? the ? incoming ? video ? signal. ? instant ? auto ? advantages: ? ? performs ? auto ? adjustments ? faster ? and ? more ? accurately ? than ? current ? conventional ? methods. ?? ? performs ? auto ? adjustments ? on ? full ? width ? and ? partial ? width ? images. ? ? performs ? auto ? adjustments ? on ? dos ? screens ? and ? moving ? images ? such ? as ? screen ? savers ? and ? motion ? pictures. ? for ? further ? information, ? refer ? to ? the ? instant ? auto ? application ? brief ? (c5621 \ apb \ 01). ? 4.19 intelligent image processing 4.19.1 horizontal and vertical shrink to ? preserve ? memory ? bandwidth, ? in ? certain ? situations ? a ? shrink ? function ? may ? be ? performed ? on ? the ? input ? data, ? prior ? to ? sending ? this ? data ? to ? the ? sdram. ?? this ? is ? an ? arbitrary ? horizontal/vertical ? reduction ? to ? between ? (50% ? + ? 1 ? pixel/line) ? to ? 100% ? of ? the ? input. ?? for ? example, ? this ? allows ? uxga ? 1600x1200 ? pixels ? to ? be ? displayed ? as ? sxga ? 1280x1024. ? this ? is ? useful ? to ? allow ? the ? user ? to ? use ? windows ? display ? properties ? to ? reduce ? the ? screen ? resolution ? if ? it ? is ? higher ? than ? that ? of ? the ? display. ? 4.19.2 variable zoom scaling the ? scaling ? engine ? uses ? an ? advanced ? multi \ tap, ? non \ linear ? scaling ? engine, ? which ? uses ? fir ? filter ? technique ? and ? can ? accept ? nearly ? any ? input ? resolution ? and ? can ? scale ? it ? to ? any ? output ? resolution, ? in ? a ? range ? from ? one \ half ? reduction ? to ? a ? 256 \ fold ? expansion. ? scaling ? is ? highly ? configurable, ? with ? options ? to ? scale ? in ? both ? horizontal ? and ? vertical ? directions ? with ? different ? methods. ? the ? scalar ? must ? scale ? nearly ? any ? signal ? input ? to ? accommodate ? nearly ? any ? panel ? input. ? moreover, ? it ? provides ? high ? quality ? scaling ? of ? real ? time ? video ? and ? graphics ? images. ? an ? input ? field/frame ? is ? scalable ? in ? both ? the ? vertical ? and ? horizontal ? dimensions. ?? interlaced ? fields ? may ? be ? spatially ? de \ interlaced ? by ? vertically ? scaling ? and ? repositioning ? the ? input ? fields ? to ? align ? with ? the ? output ? display?s ? pixel ? map. ? 4.19.3 programmable sharpening filter the ? coefficients ? used ? in ? the ? scaling ? engine ? are ? programmable ? and ? can ? be ? used ? to ? perform ? sharpening. ? for ? example, ? font ? edges ? can ? be ? enhanced ? in ? text ? or ? spreadsheet ? applications, ? or ? motion ? video ? images ? can ? be ? sharpened. ? this ? is ? available ? at ? any ? scale ? factor, ? or ? when ? scaling ? is ? not ? required ? (i.e. ? 1:1 ? mode). ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 35 4.19.4 non-linear scaling (panoramic) the ? input ? image ? is ? separated ? into ? three ? zones ? horizontally; ? left, ? center ? and ? right. ?? the ? center ? zone ? is ? scaled ? at ? a ? programmable ? fixed ? ratio. ?? the ? left ? and ? right ? zones ? have ? a ? programmable ? changing ? scale ? factor ? that ? changes ? from ? left ? to ? right. ? the ? function ? of ? scale ? ratio ? change ? can ? either ? be ? linear ? or ? parabolic. ? this ? feature ? is ? available ? on ? the ? main ? channel ? only. ? figure 20: non-linear scaling of a 4:3 to 16:9 aspect ratio conversion scale factor outer edge scale factor center scale factor 4:3 input image scaled 16:9 output left center right a) linear b) parabolic (anamorphic) scaling ratio change ? 4.19.5 format and aspect ratio conversion this ? device ? incorporates ? zoom/shrink ? scalers ? use ? an ? advanced ? scaling ? technique ? proprietary ? to ? genesis ? microchip ? inc., ? providing ? simultaneous ? high ? quality ? scaling ? of ? real ? time ? video ? and ? graphics ? images ? on ? both ? channels. ? an ? input ? field/frame ? is ? scalable ? arbitrarily ? in ? both ? the ? vertical ? and ? horizontal ? dimensions. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 36 4.20 advanced digital color controls the ? digital ? color ? controls ? consist ? of ? the ? components ? shown ? in ? the ? following ? figure. ? figure 21: digital color controls data path 4.20.1 adaptive contrast and color (acc) most ? video ? content ? is ? tailored ? for ? display ? on ? crts ? or ? in ? movie ? theatres. ? however, ? crt ? monitors ? have ? a ? wider ? dynamic ? range ? than ? lcd ? monitors. ? therefore, ? it ? is ? desirable ? to ? enhance ? the ? luminance ? and ? chrominance ? dynamic ? range ? when ? video ? is ? displayed ? using ? lcd ? monitors. ?? acc ? enhances ? the ? contrast ? of ? the ? image ? to ? account ? for ? this. ? this ? makes ? dark ? pixels ? darker ? and ? bright ? pixels ? brighter, ? thus ? enhancing ? the ? overall ? contrast ? of ? the ? image. ? in ? addition, ? the ? contrast ? enhancement ? is ? adaptive. ? this ? is ? done ? by ? calculating ? the ? running ? average ? of ? the ? luminance ? content ? of ? several ? images, ? divided ? up ? into ? multiple ? luminance ? ranges ? (comprising ? a ? histogram). ? this ? histogram ? is ? then ? used ? to ? select ? the ? weighting ? coefficients ? for ? the ? corresponding ? user ? programmable ? transfer ? functions. ?? the ? running ? average ? may ? be ? applied ? over ? a ? programmable ? number ? of ? frames. ? acc ? can ? be ? applied ? within ? a ? highlight ? window ? or ? over ? the ? full ? display ? area. ?? this ? allows ? for ? creating ? variety ? of ? theme ? modes ? than ? can ? be ? used ? for ? different ? viewing ? preferences ? and ? can ? be ? used ? to ? differentiate ? among ? different ? product ? brands. ? 4.20.2 active color management 3d (acm-3d) active ? color ? management ? three ? dimension ? provides ? six ? axis ? color ? controls ? to ? give ? stunning ? color ? quality. ? it ? provides ? control ? of ? global ? color ? parameters ? like ? hue, ? saturation ? and ? contrast, ? and ? local ? color ? changes ? such ? as ? skin ? tone ? adjustment, ? green ? enhance, ? or ? blue ? stretch ? without ? effecting ? overall ? color ? of ? the ? picture. ? it ? can ? be ? applied ? within ? a ? highlight ? window ? or ? over ? the ? full ? display ? area. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 37 4.20.3 3x3 matrix the ? purpose ? of ? the ? 3x3 ? matrix ? is ? to ? convert ? the ? yuv ? color ? space ? back ? into ? rgb ? color ? space ? after ? acc/acm ? processing. ?? the ? 3x3 ? matrix ? also ? allows ? for ? implementation ? of ? global ? contrast, ? brightness ? as ? well ? as ? tv \ style ? hue ? and ? saturation ? adjustments ? via ? on \ screen \ display ? menus. ? there ? are ? two ? 3x3 ? matrix ? blocks ? available, ? one ? for ? the ? main ? and ? one ? for ? the ? pip ? channel. ? since ? it ? is ? also ? possible ? that ? the ? color ? space ? inside ? and ? outside ? of ? the ? highlight ? window ? is ? different, ? two ? sets ? of ? coefficients ? are ? provided ? for ? proper ? conversion ? to ? the ? rgb ? color ? space: ? one ? for ? inside ? and ? one ? for ? outside ? of ? the ? highlight ? window. ? this ? feature ? is ? available ? for ? the ? main ? channel ? only. ? 4.20.4 color standardization and srgb support internet ? shoppers ? may ? be ? very ? picky ? about ? what ? color ? they ? experience ? on ? the ? display. ? realcolor tm ? digital ? color ? controls ? can ? be ? used ? to ? make ? the ? color ? response ? of ? an ? lcd ? monitor ? compliant ? with ? standard ? color ? definitions, ? such ? as ? srgb. ? srgb ? is ? a ? standard ? for ? color ? exchange ? proposed ? by ? microsoft ? and ? hp ? (see ? www.srgb.com) . ? realcolor ? controls ? can ? be ? used ? to ? make ? lcd ? monitors ? srgb ? compliant, ? even ? if ? the ? native ? response ? of ? the ? lcd ? panel ? itself ? is ? not. ? for ? more ? information ? on ? srgb ? compliance ? using ? genesis ? devices ? please ? refer ? to ? the ? srgb ? application ? brief ? c5115 \ apb \ 02a. ? 4.20.5 video windowing often ? video ? content ? (e.g. ? movie ? from ? dvd) ? is ? displayed ? in ? a ? portion ? of ? the ? display ? while ? the ? operating ? system?s ? desktop ? appears ? in ? the ? remainder. ? in ? this ? case ? it ? is ? desirable ? to ? have ? different ? color ? controls ? in ? the ? various ? regions ? of ? the ? display. ? for ? example, ? the ? user ? may ? desire ? that ? the ? desktop ? is ? srgb ? compliant ? while ? performing ? hue ? or ? saturation ? adjustments ? in ? the ? region ? containing ? the ? video ? content. ? to ? perform ? such ? adjustments ? the ? 3x3 ? color ? controls ? and ? the ? gamma ? tables ? may ? be ? separately ? controlled ? inside ? and ? outside ? a ? defined ? rectangle. ? the ? coordinates ? of ? the ? rectangle ? may ? be ? provided ? by ? the ? operating ? system ? (and ? communicated ? using ? ddc2bi) ? or ? selected ? by ? the ? user ? (using ? the ? osd). ? 4.21 video enhancement 4.21.1 enhancement filters this ? device ? provides ? image ? enhancement ? filters ? to ? enhance ? high ? frequency ? components ? in ? the ? video ? processing ? channel. ? different ? levels ? of ? sharpening ? can ? be ? implemented ? by ? selecting ? different ? programmable ? coefficients ? for ? the ? horizontal ? sharpening ? filters. ??? 4.21.2 lcd response time compensation liquid ? crystal ? material ? speeds ? differ ? between ? panels ? and ? the ? technologies ? of ? driving ? each ? panel ? vary, ? a ? unique ? look ? up ? table ? (lut) ? is ? required ? for ? each ? panel ? for ? optimum ? response ? time ? calibration. ?? the ? lcd ? overdrive ? processor ? is ? a ? recursive ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 38 technology ? based ? compensation ? for ? poor ? liquid ? crystal ? response ? time. ?? this ? is ? to ? prevent ? smearing ? of ? video ? images ? which ? require ? image ? change ? response ? times ? at ? the ? same ? or ? faster ? rate ? than ? that ? of ? the ? incoming ? video ? frame ? rate ? of ? 50 ? or ? 60 ? hz. ? based ? on ? the ? measurement ? of ? the ? lcd ? panel ? chosen ? for ? the ? display, ? a ? look ? up ? table ? will ? be ? generated ? for ? every ? type ? of ? panel. ?? this ? look ? up ? table ? is ? calibrated ? for ? each ? individual ? panel ? to ? create ? a ? unique ? compensation ? for ? each ? different ? lcd ? panel ? figure 22: lcd response time compensation lcd overdrive processing frame buffer previous frame data current frame data input data stream panel response time compensated data 4.22 external memory interface the ? external ? memory ? interface ? controls ? the ? access ? to ? the ? single ? data ? rate ? (sdr) ? sdram ? for ? the ? pip ? display ? window, ? the ? frame ? rate ? converter, ? response ? time ? compensator ? and ? aspect ? ratio ? converter. ? an ? arbitrator ? controls ? the ? write ? and ? read ? operations ? based ? on ? the ? status ? of ? the ? fifos ? present ? at ? each ? read ? and ? write ? channel, ? ensuring ? that ? underflow ? of ? fifos ? do ? not ? occur. ?? adequate ? depths ? of ? the ? fifos ? ensure ? no ? overflow ? occurs. ?? 32mbits ? of ? sdram ? memory ? is ? required ? for ? full ? functionality ? of ? the ? chip. ? the ? external ? memory ? interface ? supports ? one ? or ? two ? 1m ? x ? 16 ? sdr ? sdrams. ? the ? external ? memory ? interface ? supports ? sdram ? operation ? speeds ? up ? to ? 187mhz. ?? please ? refer ? to ? application ? note ? c5961 \ apn \ 01. ? this ? application ? note ? covers ? details ? about ? different ? video ? features ? and ? image ? enhancements ? that ? can ? be ? enabled ? depending ? on ? the ? external ? memory ? configurations ? (memory ? capacity, ? speed ? and ? bandwidth), ? input ? and ? output ? resolutions. ? 4.22.1 supported sdr devices this ? device ? operates ? seamlessly ? with ? commercially ? available ? 1mx16 ? sdr ? sdram ? and ? 2mx32 ? sdram ? devices ? operating ? at ? 187mhz. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 39 4.22.2 adjustable frame store interface parameters a ? full ? set ? of ? registers ? is ? provided ? to ? optimize ? the ? timing ? parameters ? for ? a ? particular ? memory ? interface. ? most ? will ? not ? require ? adjustment ? as ? the ? process ? of ? initialization ? is ? automated. ? 4.23 frame rate conversion frame ? rate ? conversion ? is ? required ? when ? there ? is ? a ? difference ? between ? the ? refresh ? rates ? between ? the ? main ? and ? the ? pip ? channels. ? in ? such ? cases ? the ? frame ? rate ? of ? the ? pip ? channel ? is ? frame ? rate ? converted ? to ? match ? that ? of ? the ? main ? channel. ? another ? example ? of ? the ? frc ? is ? when ? the ? displaying ? panel ? can?t ? support ? the ? frame ? rate ? of ? the ? incoming ? video. ? for ? example ? a ? source ? with ? a ? vertical ? refresh ? rate ? of ? 75hz, ? in ? order ? to ? be ? properly ? displayed ? on ? a ? panel ? that ? can ? support ? a ? max ? of ? 60hz ? refresh ? rate, ? must ? be ? frame ? rate ? converted ? to ? 60hz ? rate. ? note: ? all ? other ? features ? are ? disabled ? if ? there ? is ? frame ? rate ? conversion ? required ? in ? the ? main ? channel. ??? 4.24 picture-in-picture ? pip channel processing this ? device ? allows ? a ? flexible ? picture \ in \ picture ? (pip) ? display ? configuration ? whereby ? either ? the ? graphics ? or ? video ? channel ? may ? act ? as ? the ? pip ? source ? to ? overlay ? over ? the ? other ? channel. ? any ? one ? of ? the ? inputs ? (dual ? inputs ? to ? the ? adc, ? dvi, ? dip) ? may ? be ? multiplexed ? to ? either ? channel. ?? the ? pip ? display ? window ? can ? be ? placed ? arbitrarily ? in ? the ? main ? display ? window. ?? the ? size ? of ? the ? pip ? display ? window ? is ? fully ? programmable ? up ? to ? 640x480 ? pixels. ? the ? pip ? display ? allows ? 16 ? levels ? of ? blending ? within ? the ? pip ? window ? either ? with ? a ? specified ? background ? color ? or ? the ? main ? channel. ?? this ? device ? can ? support ? viewing ? of ? both ? video ? and ? graphics ? in ? a ? side \ by \ side ? format. ? the ? maximum ? widow ? size ? for ? the ? side \ by \ side ? is ? 960x600 ? pixels ? each. ? in ? this ? mode, ? the ? video ? input ? will ? always ? be ? processed ? by ? the ? main ? channel ? while ? the ? graphics ? input ? will ? be ? processed ? by ? the ? pip ? channel. ???? using ? external ? memory, ? the ? pip ? channel ? image ? data ? can ? be ? frame ? rate ? converted ? so ? that ? it ? matches ? the ? refresh ? rate ? of ? the ? main ? image ? and ? can ? subsequently ? be ? merged ? in ? various ? picture ? arrangements. ? the ? pip ? channel ? contains ? a ? separate ? 3x3 ? color ? matrix ? to ? allow ? for ? different ? color ? settings ? in ? the ? pip ? channel ? from ? the ? main ? channel. ? 4.24.1 pip border and blending the ? pip ? display ? mode ? consists ? of ? two ? windows ? with ? one ? smaller ? window ? sitting ? on ? top ? of ? the ? other. ?? this ? smaller ? window ? is ? called ? the ? pip ? window. ?? its ? size ? and ? position ? are ? fully ? programmable ? up ? to ? 640x480 ? pixels. ?? the ? transparency ? (blend) ? level ? of ? the ? pip ? window ? is ? adjustable ? up ? to ? 16 ? levels. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 40 figure 23: pip example 1 2 1 2 no blend (opaque) blended this ? device ? incorporates ? hardware ? support ? for ? the ? pip \ border. ? the ? pip ? border ? size, ? color ? and ? on/off ? status ? is ? programmable. ?? 4.25 output display port (odp) the ? output ? display ? port ? provides ? data ? and ? control ? signals ? that ? permit ? this ? device ? to ? connect ? to ? a ? variety ? of ? flat ? panel ? devices ? using ? a ? dual ? channel ? lvds ? / ? 24 \ bit ? ttl ? interface. ?? the ? output ? interface ? is ? configurable ? for ? single ? or ? dual ? wide ? lvds ? in ? 18 ? or ? 24 \ bit ? rgb ? pixels ? format. ? all ? display ? data ? and ? timing ? signals ? are ? synchronous ? with ? the ? dclk ? display ? clock. ? the ? integrated ? lvds ? transmitter ? is ? programmable ? to ? allow ? the ? data ? and ? control ? signals ? to ? be ? mapped ? into ? any ? sequence ? depending ? on ? the ? specified ? receiver ? format. ? dc ? balanced ? operation ? is ? supported ? as ? described ? in ? the ? open ? ldi ? standard. ? 4.25.1 display synchronization display synchronization mode support: ? frame ? sync ? mode: ? the ? display ? frame ? rate ? is ? synchronized ? to ? the ? input ? frame ? or ? field ? rate. ? this ? mode ? is ? used ? for ? standard ? operation. ? ? free ? run ? mode: ? no ? synchronization. ? this ? mode ? is ? used ? when ? there ? is ? no ? valid ? input ? timing ? (i.e. ? to ? display ? osd ? messages ? or ? a ? splash ? screen) ? or ? for ? testing ? purposes. ? in ? free \ run ? mode, ? the ? display ? timing ? is ? determined ? only ? by ? the ? values ? programmed ? into ? the ? display ? window ? and ? timing ? registers. ? 4.25.2 display timing programming horizontal ? values ? are ? programmed ? in ? single \ pixel ? increments ? relative ? to ? the ? leading ? edge ? of ? the ? horizontal ? sync ? signal. ?? vertical ? values ? are ? programmed ? in ? line ? increments ? relative ? to ? the ? leading ? edge ? of ? the ? vertical ? sync ? signal. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 41 figure 24: display windows and timing display active window display background window vertical blanking (back porch) vsync region horizontal blanking (back porch) hsync region dv_vs_end den ** dhs dv_bkgnd_start dv_active_start dv_active_length dvs dv_bkgnd_end dv_total dh_hs_end dh_bkgnd_start dh_bkgnd_end dh_total dh_active_start dh_active_width vertical blanking (front porch) horizontal blanking (front porch) ** den is not asserted during vertical blanking 4.25.3 gamma look-up table (lut) each ? pixel ? of ? a ? displayed ? cell ? is ? resolved ? to ? an ? 8 \ bit ? color ? code. ? an ? 8 ? to ? 10 \ bit ? look \ up ? table ? (lut) ? for ? each ? input ? color ? channel ? is ? intended ? for ? gamma ? correction ? and ? to ? compensate ? for ? a ? non \ linear ? response ? of ? the ? lcd ? panel. ? a ? 10 \ bit ? output ? minimizes ? the ? quantization ? errors ? in ? dark ? luminance ? ranges ? ensuring ? more ? accurate ? color ? representation. ?? the ? lut ? is ? user \ programmable ? to ? provide ? an ? arbitrary ? transfer ? function. ? gamma ? correction ? occurs ? after ? the ? zoom ? / ? shrink ? scaling ? block. ? if ? bypassed, ? the ? lut ? does ? not ? require ? programming. ? 4.25.4 output dithering the ? gamma ? lut ? outputs ? a ? 10 \ bit ? value ? for ? each ? color ? channel. ? this ? value ? is ? dithered ? down ? to ? either ? 8 \ bits ? for ? 24 \ bit ? per ? pixel ? panels, ? or ? 6 \ bits ? for ? 18 \ bit ? per ? pixel ? panels. ? in ? this ? way ? it ? is ? possible ? to ? display ? 16.7 ? million ? colors ? on ? a ? lcd ? panel ? with ? 6 \ bit ? column ? drivers. ? the ? benefit ? of ? dithering ? is ? that ? the ? eye ? tends ? to ? average ? neighboring ? pixels ? and ? a ? smooth ? image ? free ? of ? contours ? is ? perceived. ? dithering ? works ? by ? spreading ? the ? quantization ? error ? over ? neighboring ? pixels ? both ? spatially ? and ? temporally. ? two ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 42 dithering ? algorithms ? are ? available: ? random ? or ? ordered ? dithering. ? ordered ? dithering ? is ? recommended ? when ? driving ? a ? 6 \ bit ? panel. ? all ? gray ? scales ? are ? available ? on ? the ? panel ? output ? whether ? using ? 8 \ bit ? panel ? (dithering ? from ? 10 ? to ? 8 ? bits ? per ? pixel) ? or ? using ? 6 \ bit ? panel ? (dithering ? from ? 10 ? down ? to ? 6 ? bits ? per ? pixel). ? 4.25.5 lvds transmitter two ? lvds ? channels ? (a ? and ? b) ? are ? available ? to ? transmit ? data ? and ? timing ? information ? to ? the ? display ? device. ? note: ?? for ? single ? wide ? lvds ? usage ? the ? lvds ? even ? channel ? must ? be ? used. ? the ? following ? tables ? show ? the ? available ? lvds ? mappings. ? an ? integrated ? lvds ? transmitter ? with ? programmable ? input ? to ? output ? configuration ? is ? provided ? to ? enable ? drive ? of ? all ? known ? panels. ? the ? lvds ? transmitter ? can ? support ? the ? following: ? ? single ? pixel ? mode ? ? 24 \ bit ? panel ? mapping ? to ? the ? lvds ? channels ? ? 18 \ bit ? panel ? mapping ? to ? the ? lvds ? channels ?? ? programmable ? channel ? swapping ? (the ? clocks ? are ? fixed) ? ? programmable ? channel ? polarity ? swapping ? table 22: supported lvds 24-bit panel data mappings channel 0 r0, r1, r2, r3, r4, r5, g0 channel 1 g1, g2, g3, g4, g5, b0, b1 channel 2 b2, b3, b4, b5, phs, pvs, pde channel 3 r6, r7, g6, g7, b6, b7, res channel 0 r2, r3, r4, r5, r6, r7, g2 channel 1 g3, g4, g5, g6, g7, b2, b3 channel 2 b4, b5, b6, b7, phs, pvs, pde channel 3 r0, r1, g0, g1, b0, b1, res table 23: supported lvds 18-bit panel data mapping channel 0 r0, r1, r2, r3, r4, r5, g0 channel 1 g1, g2, g3, g4, g5, b0, b1 channel 2 b2, b3, b4, b5, phs, pvs, pde channel 3 disabled for this mode ? the ? lvds ? transmitter ? may ? be ? configured ? to ? operate ? in ? dc ? and ? non \ dc ? balance ? mode. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 43 4.25.6 single pixel ttl output figure 25: single pixel width display data dclk (output) den (output) rgb0 rgb4 rgb3 rgb2 rgb1 er/eg/eb (output) xxx 4.25.7 panel power sequencing (ppwr, pbias) two ? dedicated ? outputs ? ppwr ? and ? pbias ? are ? used ? to ? control ? lcd ? power ? sequencing ? once ? data ? and ? control ? signals ? are ? stable. ? the ? timing ? of ? these ? signals ? is ? fully ? programmable. ? figure 26: panel power sequencing ppwr output panel data and control signals pbias output tmg1 tmg2 tmg3 tmg4 power_seq_en = 1 power_seq_en = 0 4.26 energy spectrum management? (esm) high ? spikes ? in ? the ? emi ? power ? spectrum ? may ? cause ? lcd ? monitor ? products ? to ? violate ? emissions ? standards. ? this ? device ? has ? many ? features ? that ? can ? be ? used ? to ? reduce ? electromagnetic ? interference ? (emi). ? these ? include ? drive ? strength ? control ? and ? clock ? spectrum ? modulation. ? these ? features ? help ? to ? eliminate ? the ? costs ? associated ? with ? emi ? reducing ? components ? and ? shielding. ? 4.27 on-screen display (osd) this ? device ? incorporates ? a ? fully ? programmable, ? high \ quality ? osd ? controller. ? the ? graphics ? are ? divided ? into ? ?cells? ? of ? programmable ? size. ? the ? cells ? are ? stored ? in ? an ? on \ free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 44 chip ? static ? ram ? (16k ? bytes) ? and ? can ? be ? stored ? as ? 1 \ bit ? per ? pixel ? data, ? 2 \ bit ? per ? pixel ? data ? or ? 4 \ bit ? per ? pixel ? data. ? some ? general ? features ? of ? the ? osd ? controller ? include: ? ? two ? osd ? rectangles ? ? ? the ? osd ? can ? appear ? in ? two ? separately ? defined ? rectangular ? regions. ? ? osd ? position ? ? ? the ? osd ? menu ? can ? be ? positioned ? anywhere ? on ? the ? display ? region. ? the ? reference ? point ? is ? horizontal ? and ? vertical ? display ? background ? start ? (dh_bkgnd_start ? and ? dv_bkgnd_start). ? ? osd ? stretch ? ? ? the ? osd ? image ? can ? be ? stretched ? horizontally ? and/or ? vertically ? by ? a ? factor ? of ? two. ? pixel ? and ? line ? replication ? is ? used ? to ? stretch ? the ? image. ?? ? osd ? blending ? ? ? sixteen ? levels ? of ? blending ? are ? supported ? for ? selected ? colors ? in ? the ? character \ mapped. ? 4.27.1 on-chip osd sram the ? on \ chip ? static ? ram ? (32k ? bytes) ? stores ? the ? cell ? map, ? cell ? definitions, ? and ? attribute ? map. ? the ? osd ? sram ? is ? shared ? by ? the ? on \ chip ? microcontroller ? as ? part ? of ? its ? normal ? addressable ? memory ? space. ? in ? memory, ? the ? cell ? map ? is ? organized ? as ? an ? array ? of ? words, ? each ? defining ? the ? attributes ? of ? one ? visible ? character ? on ? the ? screen ? starting ? from ? upper ? left ? of ? the ? visible ? character ? array. ? these ? attributes ? specify ? which ? character ? to ? display, ? whether ? it ? is ? stored ? as ? 1, ? 2 ? or ? 4 ? bits ? per ? pixel, ? the ? foreground ? and ? background ? colors, ? blinking, ? etc. ? registers ? are ? used ? to ? define ? the ? visible ? area ? of ? the ? osd ? image. ? figure 27: osd cell map osd_r_heigh t osd_r_width address 1: cell attributes for upper-left hand cell address 25: attributes for upper-right hand cell address26: cell attributes for 1 st cell, 2 nd row brightness contrast cell ? definitions ? are ? stored ? as ? bit ? map ? data. ? on \ chip ? registers ? point ? to ? the ? start ? of ? 1 \ bit ? per ? pixel ? definitions, ? 2 \ bit ? per ? pixel ? definitions ? and ? 4 \ bit ? per ? pixel ? definitions ? respectively. ? note ? that ? the ? cell ? map ? and ? the ? cell ? definitions ? share ? the ? same ? on \ chip ? ram. ? thus, ? the ? size ? of ? the ? cell ? map ? can ? be ? traded ? off ? against ? the ? number ? of ? different ? cell ? definitions. ? in ? particular, ? the ? size ? of ? the ? osd ? image ? and ? the ? number ? of ? cell ? definitions ? must ? fit ? in ? ram. ?? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 45 4.28 on-chip microcontroller (ocm) the ? ocm ? executes ? a ? firmware ? program ? running ? from ? external ? serial ? peripheral ? interface ? (spi) ? rom. ? a ? serial ? peripheral ? interface ? is ? provided ? for ? use ? with ? a ? serial ? flash ? rom ? and ? a ? cache ? controller ? inside ? the ? device. ? this ? port ? connects ? directly ? to ? standard, ? commercially ? available ? spi ? rom ? or ? programmable ? spi ? flash ? rom ? devices. ? spi ? flash ? roms ? up ? to ? 512kb ? is ? supported. ? 4.28.1 in-system-programming (i sp) of external flash rom in ? is ? possible ? to ? program ? the ? serial ? rom ? devices ? via ? the ? standard ? uart ? or ? by ? using ? ddc2bi ? protocol. ? hardware ? is ? provided ? by ? genesis ? microchip ? to ? interface ? the ? programming ? host ? with ? the ? system ? being ? programmed. ? the ? embedded ? boot ? firmware ? (see ? the ? embedded ? bootstrap ? function ? section) ? performs ? the ? programming ? of ? external ? flash ? rom. ? 4.28.2 serial peripheral interface for spi flash rom this ? device ? supports ? spi ? serial ? flash ? rom ? up ? to ? 4m \ bits ? through ? spi ? pins, ? spi_csn, ? spi_clk, ? spi_do ? and ? spi_di. ? the ? spi ? interface ? should ? be ? configured ? as ? follows. ? spi_csn ? < \ > ?? ce# ? of ? spi ? rom ? spi_clk ? < \ > ?? sck ? of ? spi ? rom ? spi_do ?? < \ > ?? si ? of ? spi ? rom ? spi_di ??? < \ > ?? so ? of ? spi ? rom ? pins ? of ? wp# ? and ? hold# ? of ? spi ? rom ? are ? options ? for ? controlling ? the ? spi ? rom. ? wp# ? if ? pulled ? low ? will ? disable ? writing ? to ? the ? rom. ? hold# ? is ? used ? when ? multiple ? devices ? are ? used ? in ? daisy \ chain ? configuration. ? they ? can ? be ? pulled \ high ? all ? the ? time ? to ? disable ? their ? functions ? or ? they ? can ? be ? controlled ? with ? gpios ? for ? more ? flexibility. ? refer ? to ? spi ? rom ? specifications ? for ? details. ?? 4.28.3 uart interface the ? ocm ? has ? an ? integrated ? universal ? asynchronous ? remote ? terminal ? (uart) ? port ? that ? can ? be ? used ? as ? a ? factory ? debug ? port. ? in ? particular, ? the ? uart ? can ? be ? used ? to ? 1) ? read ? / ? write ? chip ? registers, ? 2) ? read ? / ? write ? to ? nvram, ? and ? 3) ? read ? / ? write ? to ? flash ? rom ? (in \ system \ programming). ? 4.28.4 ddc2bi interface hardware ? support ? is ? provided ? for ? ddc2bi ? communication ? over ? the ? ddc ? channel ? of ? either ? the ? analog ? or ? dvi ? input ? ports. ? the ? specification ? for ? the ? ddc2bi ? standard ? can ? be ? obtained ? from ? vesa ? ( www.vesa.org) . ? the ? ddc2bi ? port ? can ? be ? used ? as ? a ? factory ? debug ? port ? or ? for ? field ? programming. ? in ? particular, ? the ? ddc2bi ? port ? can ? be ? used ? to ? 1) ? read ? / ? write ? chip ? registers, ? 2) ? read ? / ? write ? to ? nvram, ? and ? 3) ? read ? / ? write ? to ? flash ? rom ? (in \ system \ programming). ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 46 the ? factory ? programming ? or ? test ? station ? connects ? to ? this ? device ? through ? the ? direct ? data ? channel ? (ddc) ? of ? the ? dsub15 ? or ? dvi ? connectors. ? for ? example, ? the ? pc ? can ? make ? display ? test ? patterns ? (see ? the ? test ? pattern ? generator ? section) ? a ? camera ? can ? be ? used ? to ? automate ? the ? calibration ? of ? the ? lcd ? panel. ? two ? pairs ? of ? pins ? are ? available ? for ? ddc2bi ? communication. ? for ? ddc2bi ? communication ? over ? the ? analog ? vga ? connector ? pins ? ddc_scl_ch1 ? and ? ddc_sda_ch1 ? should ? be ? connected ? to ? the ? ddc ? clock ? and ? data ? pins ? of ? the ? analog ? dsub15 ? vga ? connector. ? for ? ddc2bi ? communication ? over ? the ? dvi ? connector ? pins ? ddc_scl_ch2 ? and ? ddc_sda_ch2 ? should ? be ? connected ? to ? the ? ddc ? clock ? and ? data ? pins ? of ? the ? dvi ? connector. ? this ? device ? contains ? serial ? to ? parallel ? conversion ? hardware ? that ? is ? then ? accessed ? by ? firmware ? for ? interpretation ? and ? execution ? of ? the ? ddc2bi ? command ? set. ? note ? that ? ddc2bi ? can ? only ? be ? activated ? on ? only ? one ? of ? the ? inputs ? at ? a ? time. ? the ? port ? activated ? by ? default ? is ? specified ? using ? the ? bootstrap ? value ? of ? boot[3]/icd_sel. ? firmware ? may ? overwrite ? the ? default ? setting ? by ? register ? programming. ? 4.28.5 jtag interface a ? jtag ? interface ? is ? provided ? to ? allow ? in \ circuit ? firmware ? debugging. ? this ? is ? done ? using ? a ? jtag ? port. ? this ? port ? is ? available ? on ? the ? following ? signals: ? ? jtag_reset ??? ? jtag_tdo ?? ? ? jtag_tdi ?? ? ? host_scl ? (jtag_clk) ? ? host_sda ? (jtag_mode) ? also, ? a ? 2 \ wire ? to ? jtag ? bridge ? circuit ? is ? provided ? to ? allow ? jtag ? commands ? to ? be ? issued ? using ? only ? two ? pins ? host_scl ? and ? host_sda. ? 4.28.6 general purpose inputs and outputs (gpio) there ? are ? 49 ? potential ? general \ purpose ? input/output ? (gpio) ? pins. ? not ? all ? may ? be ? available ? depending ? on ? shared ? functionality ? of ? particular ? pins. ? these ? are ? used ? by ? the ? ocm ? to ? communicate ? with ? other ? devices ? in ? the ? system ? such ? as ? keypad ? buttons, ? nvram, ? led?s, ? audio ? dac, ? etc. ? each ? gpio ? has ? independent ? direction ? control ? and ? open ? drain ? enable ? for ? reading ? and ? writing. ?? note ? that ? some ? gpio ? pins ? have ? alternate ? functionality. ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 47 table 24: gpio and alternate functions pin name pin number alternate function gpio_23/int0 214 interrupt input 0. [5v-tolerant, internal pull-down] gpio_24/vda[0] 215 656 video data[0]. [5v-tolerant, internal pull-down] gpio_25/vda[1] 216 656 video data[1]. [5v-tolerant, internal pull-down] gpio_26/vda[2] 217 656 video data[2]. [5v-tolerant, internal pull-down] gpio_27/vda[3] 218 656 video data[3]. [5v-tolerant, internal pull-down] gpio_28/vda[4] 219 656 video data[4]. [5v-tolerant, internal pull-down] gpio_29/vda[5] 220 656 video data[5]. [5v-tolerant, internal pull-down] gpio_30/vda[6] 221 656 video data[6]. [5v-tolerant, internal pull-down] gpio_31/vda[7] 222 656 video data[7]. [5v-tolerant, internal pull-down] gpio_10/b4 108 lvttl display port blue 4; [5v-tolerant, internal pull-down] gpio_11/b5 109 lvttl display port blue 5; [5v-tolerant, internal pull-down] gpio_12/b6 110 lvttl display port blue 6; [5v-tolerant, internal pull-down] gpio_13/b7 111 lvttl display port blue 7; [5v-tolerant, internal pull-down] gpio_14/dclk 115 lvttl display port dclk; [5v-tolerant, internal pull-down] gpio_15/den 116 lvttl display port den; [5v-tolerant, internal pull-down] gpio_16/dhs 117 lvttl display port dhs [5v-tolerant, internal pull-down] gpio_17/dvs 118 lvttl display port dvs [5v-tolerant, internal pull-down] gpio_18/ scl_0(2w_mst) 119 two_wire master_0 clock [schmitt trigger, 5v-tolerant] gpio_19/sda_0(2w_mst) 120 two_wire master_0 data [schmitt trigger, 5v-tolerant] gpio_20/scl_1(2w_mst) 121 two_wire master_1 clock [schmitt trigger, 5v-tolerant] gpio_21/sda_1(2w_mst) 122 two_wire master_1 data [schmitt trigger, 5v-tolerant] gpio_7/jtag_mode 157 jtag boundary scan mode [5v-tolerant, internal pull-up] gpio_6/jtag_clk 158 jtag boundary scan clk [5v-tolerant, internal pull-up] gpio_5/jtag_tdi 159 jtag boundary scan tdi [5v-tolerant, in ternal pull-up] gpio_4/jtag_tdo 160 jtag boundary scan tdo [5v-tolerant, internal pull-up] gpio_3/jtag_reset 163 jtag boundary scan reset [5v-tolerant, internal pull-up] gpio_2 164 no alternative functions. [5v-tolerant, internal pull-down] gpio_49 165 no alternative functions [open drain 5v-tolerant] gpio_48 166 no alternative functions [open drain, 5v-tolerant] gpio_22/int1 211 interrupt input 1 and also shared with interrupt out [5v-tolerant, internal pull-down] gpio_23/int0 214 interrupt input 0 [5v-tolerant, internal pull-down] gpio_0/ddc_scl_0 230 two_wire slave (ddc2b) clock input. [schmitt trigger, 5v-tolerant] gpio_1/ddc_sda_0 231 two_wire slave (ddc2b) data i/o. [schmitt trigger, 5v-tolerant] gpo_8/pwm2/boot[6] 243 pwm2 output; shared with boot[6] input. [5v-tolerant, internal pull-down] gpo_9/pwm3/boot[7] 244 pwm3 output, shared with boot[7] input [5v-tolerant, internal pull-down] gpo_0 69 no alternative functions. [5v-tolerant, internal pull-down] gpo_1 70 no alternative functions. [5v-tolerant, internal pull-down] gpo_2 71 no alternative functions. [5v-tolerant, internal pull-down] gpo_3 72 no alternative functions. [5v-tolerant, internal pull-down] gpo_4 74 no alternative functions. [5v-tolerant, internal pull-down] gpo_5 75 no alternative functions. [5v-tolerant, internal pull-down] gpo_6 77 no alternative functions. [5v-tolerant, internal pull-down] gpo_7 126 no alternative functions. [5v-tolerant, internal pull-down] itu601_4/gpio_36 2 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_3/gpio_35 3 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_2/gpio_34 4 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 48 itu601_1/gpio_33 5 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_0/gpio_32 6 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_15/gpio_47 239 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_14/gpio_46 240 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_13/gpio_45 248 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_12/gpio_44 249 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_11/gpio_43 250 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_10/gpio_42 251 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_9/gpio_41 252 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_8/gpio_40 253 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_7/gpio_39 254 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_6/gpio_38 255 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] itu601_5/gpio_37 256 itur-bt601 yuv4:2:2 input. [5v-tolerant, internal pull-down] 4.28.7 pulse width modulation (pwm) many ? of ? today?s ? lcd ? back ? light ? inverters ? require ? both ? a ? pwm ? input ? and ? variable ? dc ? voltage ? to ? minimize ? flickering ? (due ? to ? the ? interference ? between ? panel ? timing ? and ? inverter?s ? ac ? timing), ? and ? adjust ? brightness. ?? there ? are ? four ? pins ? available ? for ? pwm ? outputs: ? pwm0, ? pwm1, ? pwm2 ? and ? pwm3. ? the ? duty ? cycle ? of ? these ? signals ? is ? programmable. ? they ? may ? be ? connected ? to ? an ? external ? rc ? integrator ? to ? generate ? a ? variable ? dc ? voltage ? for ? a ? lcd ? back ? light ? inverter. ? panel ? hsync ? is ? used ? as ? the ? clock ? for ? a ? counter ? generating ? this ? output ? signal. ? pwm0 ? has ? an ? additional ? option ? for ? 10 \ bit ? duty ? cycle ? control. ? 4.28.8 low-bandwidth adc (lbadc) a ? general \ purpose ? adc ? is ? integrated ? to ? allow ? for ? functions ? such ? as ? keypad ? scanning ? or ? for ? monitoring ? system ? temperature ? or ? voltage ? sensors. ?? the ? adc ? has ? 8 ? bits ? of ? resolution, ? and ? can ? perform ? a ? conversion ? in ? 13 ? lbadc ? clock ? periods. ? the ? lbadc ? sampling ? clock ? can ? either ? be ? tclk, ? tclk/2 ? or ? tclk/4. ? the ? maximum ? sampling ? clock ? frequency ? for ? 8 \ bit ? resolution ? is ? 14mhz. ? an ? analog ? multiplexer ? selects ? one ? of ? three ? analog ? input ? pins ? as ? the ? input ? to ? the ? adc. ? figure 28: typical keypad function vcc to lbadc_return r r r r r to lbadc in ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 49 4.28.9 low power state this ? device ? provides ? a ? low ? power ? state ? in ? which ? the ? clocks ? to ? selected ? parts ? of ? the ? chip ? may ? be ? disabled. ? in ? addition, ? the ? ocm_clk ? may ? be ? reduced ? (by ? a ? factor ? of ? up ? to ? 510) ? so ? that ? the ? ocm ? itself ? consumes ? less ? power. ? 4.29 electrostatic discharge (esd) integrated ? esd ? diodes ? protect ? the ? device ? during ? handling. ? external ? on \ board ? esd ? diodes ? are ? required ? on ? the ? analog ? rgb ? inputs, ? dvi ? inputs, ? and ? ddc ? inputs ? for ? protection ? against ? electrical ? overstress ? (eos). ? ? free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 50 5 electrical specifications 5.1 preliminary dc characteristics table 25: absolute maximum ratings parameter symbol min typ max units 3.3v supply voltages (1,2) v vdd_3.3 -0.3 3.4 v 1.8v supply voltages (1.2) v vdd_1.8 -0.3 1.85 v input voltage (5v tolerant inputs) (1,2) v in5vtol -0.3 5.5 v input voltage (non 5v tolerant inputs) (1,2) v in -0.3 3.6 v electrostatic discharge v esd 2.0 kv latch-up i la 100 ma ambient operating temperature t a 0 70 c storage temperature t stg -40 150 c operating junction temp. t j 0 125 c thermal resistance (junction to air) natural convection heat slug incorporated. GM5862H/5822h on 4-layer pcb ja_4l 14.7 c/w thermal resistance (junction to case) convection heat slug incorporated. GM5862H/5822h on 4-layer pcb jc_4l 5.9 c/w soldering temperature t sol 2505 c note (1): all voltages are measured with respect to gnd. note (2): absolute maximum voltage ranges are for transient voltage excursions. table 26: dc characteristics parameter symbol min typ max units power power consumption @ 193.25 mhz (GM5862H) p wuxga 2.5 w power consumption @ 146.25 mhz (gm5822h) p wsxga+ 2.1 w power consumption @ low power mode (1) p lp <100 mw 3.3v supply voltages (vdda and rvdd) v vdd_3.3 3.2 3.3 3.4 v 1.8v supply voltages (vdd and cvdd) v vdd_1.8 1.75 1.8 1.85 v supply current @ clk =193.25 mhz ? 1.8v digital supply (2) ? 3.3v digital supply (4) ? 3.3v analog supply (5) i i vdd_1.8 i vdd_3.3 i vdda_3.3 600 110 280 ma supply current @ low power mode i lp <30 ma inputs high voltage v ih 2.0 v dd v low voltage v il gnd 0.8 v high current (v in = 5.0 v) i ih -25 25 a low current (v in = 0.8 v) i il -25 25 a capacitance (v in = 2.4 v) c in 8 pf outputs high voltage (i oh = 7 ma) v oh 2.4 v dd v low voltage (i ol = -7 ma) v ol gnd 0.4 v tri-state leakage current i oz -25 25 a note (1): low power figures result from setting the adc, dvi, and clock power down bits so that only the micro- controller is running. note (2): includes all cvdd_1.8, vdd_rpll_1.8, vdd_dvi_1.8 and vdd1_adc_1,8 pins. note (3): includes all rvdd_3.3 pins. note (4): includes pins avdd_lv_3.3, avdd_out_lv_3.3, vdda_dvi_3.3, vdda_adc, avdd_rpll_3.3 and lbadc_vdd_3.3. note (5): maximum current figures are provided for the purposes of selecting a power supply circuit. free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 51 5.2 preliminary ac characteristics all ? timings ? are ? measured ? relative ? to ? a ? 1.5v ? logic \ switching ? threshold, ? under ? normal ? operating ? conditions, ? and ? with ? loading ? capacitance ? c l ? = ? 16pf ? for ? all ? outputs. ??? table 27: maximum speed of operation clock domain max speed of operation main input clock (tclk) 25 mhz (14.3mhz recommended) dvi differential input clock (dvi_clk) 165 mhz adc clock (sclk) 205 mhz input clock (ip_clk) 195 mhz reference clock (rclk) 220mhz (200mhz recommended) on-chip microcontroller clock (ocm_clk) 100 mhz display clock (dclk) 165 mhz figure 29: timing diagram for itu656 video port vclk vdata ts vclk pl ts vclk ph t vp su t vp hd table 28: input timing for itu656 video port symbol parameter min max units t vp_su setup time for data signals valid before vclk edge. vclk edge is programmable to be either rising or falling. 2 nsec t vp_hd hold time for data/control signals to remain valid after vclk edge. 1 nsec t vclk_ph vclk high pulse width period 3 nsec t vclk_pl vclk low pulse width period 3 nsec f vclk vclk maximum operating frequency. 28 mhz free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 52 table 29: spi interface timing, vdd = 2.7~3.6v symbol parameter min max units f clk serial clock frequency 50 mhz t sckh serial clock high time 5 ns t sckl serial clock low time 5 ns t sckr serial clock rise time 5 ns t sckf serial clock fall time 5 ns t ces ce# active setup time 10 ns t ceh ce# active hold time 10 ns t chs ce# not active setup time 10 ns t chh ce# not active hold time 10 ns t cph ce# high time 100 ns t chz ce# high to high-z output 20 ns t clz sck low to low-z output 0 ns t ds data in setup time 5 ns t dh data in hold time 5 ns t oh output hold from sck change 0 ns t v output valid from sck 20 ns t se sector erase 25 ms t be block erase 25 ms t sce chip erase 100 ms t bp byte program 20 ms figure 30: serial interface spi rom timing diagrams rom_sdi (so) rom_csn (ce#) rom_sclk (sck) rom_sdo (si ) free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 53 figure 31: serial interface spi rom timing diagrams rom_csn (ce#) rom_sclk (sck) rom_sdo (si ) rom_sdi (so) table 30: external memory interface timing and adjustments out_timing min (mclk) typical (mclk) max (mclk) propagation delay from mclk to dq* (output) 1/16 ? 3/4 propagation delay from mclk to a* 1/16 ? 3/4 propagation delay from mclk to ras# 1/16 ? 3/4 propagation delay from mclk to cas# 1/16 ? 3/4 propagation delay from mclk to we# 1/16 ? 3/4 propagation delay from mclk to ba 1/16 ? 3/4 note: this table lists the amount of adjustment in unit of mclk that can be made to the framestore output propagation delays, in order to improve setup margin of dram write operations at the expense of hold margin on write operations and setup margin on read operations. free datasheet http:///
genesis microchip GM5862H/gm5822h preliminary datasheet c5862-dat-01c genesis microchip confidential 54 figure 32: lvds transmitter switching characteristics table 31: lvds even channels 0 to 3(1) symbol parameters e_ch0 ~ e_ch3 min typical max units tppos0 t/x output pulse position for bit 0 -0.3 0 0.3 ns tppos1 t/x output pulse position for bit 1 1.9 2.2 2.5 ns tppos2 t/x output pulse position for bit 2 4.1 4.4 4.7 ns tppos3 t/x output pulse position for bit 3 6.3 6.6 6.9 ns tppos4 t/x output pulse position for bit 4 8.5 8.8 9.1 ns tppos5 t/x output pulse position for bit 5 10.7 11.0 11.3 ns tppos6 t/x output pulse position for bit 6 f= 65 mhz 12.9 13.2 13.5 ns table 32: lvds odd channels 0 to 3(1) symbol parameters o_ch0 ~ o_ch3 min typical max units tppos0 t/x output pulse position for bit 0 -0.3 0 0.3 ns tppos1 t/x output pulse position for bit 1 1.9 2.2 2.5 ns tppos2 t/x output pulse position for bit 2 4.1 4.4 4.7 ns tppos3 t/x output pulse position for bit 3 6.3 6.6 6.9 ns tppos4 t/x output pulse position for bit 4 8.5 8.8 9.1 ns tppos5 t/x output pulse position for bit 5 10.7 11.0 11.3 ns tppos6 t/x output pulse position for bit 6 f= 65 mhz 12.9 13.2 13.5 ns note : there is +/- 200 ps variation for the measurements for even and odd channels in reference to clock. free datasheet http:///
genesis microchip gm5862/gm5822 preliminary datasheet c5862-dat-01c genesis microchip confidential 55 6 branding information figure 33: branding diagram note 1 note 2 note 6 note 3 note 4 note 5 gmxxxx [lot] [rev] [yyww] [z] [loc] [fab] pin #1 note 1: genesis logo must be prominently displayed note 2: part number font must be 2-3 sizes bigger than rest of text gm ? genesis microchip fli ? faroudja laboratories (genesis part that incorporates faroudja technology) xxxx ? alphanumeric part number note 3: lot code [lot] ? alphanumeric characters designation for lot number [rev] ? two letter designation for mask id revision note 4: assembly code [yyww] ? yy = year; ww = workweek; when package is molded or sealed [z] ? assembly company note 5: fab location code [loc] ? country of origin [fab] ? fab note 6: pin #1 location identifier ? free datasheet http:///
genesis microchip gm5862/gm5822 preliminary datasheet c5862-dat-01c genesis microchip confidential 56 7 mechanical specifications figure 34: 256-pin pqfp mechanical drawing c o o 1 seating plane c ccc a b d e2 e1 e d2 d1 d c aaa a?b d h bbb a?b d 4x 4x e b c ddd m a?b s d s c l1 a a2 a1 0.05 ? s o 2 o 3 gage plane l s r1 r2 h 0.25mm ? ? free datasheet http:///
genesis microchip gm5862/gm5822 preliminary datasheet c5862-dat-01c genesis microchip confidential 57 table 33: package dimensions millimeter inch symbol min nom max min nom max a ? ? 4.10 ? ? 0.161 a1 0.25 ? ? 0.010 ? ? a2 3.20 3.32 3.60 0.126 0.131 0.142 d 30.60 bsc. 1.205 bsc. d1 28.00 bsc. 1.102 bsc. e 30.60 bsc. 1.205 bsc. e1 28.00 bsc. 1.102 bsc. r2 0.08 ? 0.25 0.003 ? 0.010 r1 0.08 ? ? 0.003 ? ? ? 0 3.5 7 0 3.5 7 1 ? 0 ? ? 0 ? ? 2 ? 8 ref 8 ref 3 ? 8 ref 8 ref c 0.09 0.15 0.20 0.004 0.006 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 ref 0.051 ref s 0.20 ? ? 0.008 ? ? b 0.13 0.16 0.23 0.005 0.006 0.009 e 0.40 bsc. 0.016 bsc. d2 25.20 0.992 e2 25.20 0.992 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc ? 0.08 ? ? 0.003 ? ddd ? 0.07 ? ? 0.003 ? notes: ? ? dimensions d1 and e1 do not include mold protrusion. ? dimension b does not include damb ar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. ? the top package body size may be smaller than the bottom package body size. free datasheet http:///
genesis microchip gm5862/gm5822 preliminary datasheet c5862-dat-01c genesis microchip confidential 58 8 solder profiles the ? following ? is ? the ? recommended ? solder ? reflow ? profile ? for ? genesis ? microchip ? lead \ free ? qfp ? devices. ? figure 35: lead-free qfp solder reflow profile 50 100 150 200 250 1 to 5 c / sec pre-heat temperature: 165 c +/- 15c 90 +/- 30 secs 1 to 4 c / sec time above 230c: 50 secs max peak temperature* 250c + 0c/-5c < 10 secs 6c/sec ? free datasheet http:///

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